Enum cranelift_codegen::isa::x64::Inst

source · 
pub enum Inst {

Show 103 variants    Nop {
        len: u8,
    },
    AluRmiR {
        size: OperandSize,
        op: AluRmiROpcode,
        src1: Gpr,
        src2: GprMemImm,
        dst: WritableGpr,
    },
    AluRM {
        size: OperandSize,
        op: AluRmiROpcode,
        src1_dst: SyntheticAmode,
        src2: Gpr,
    },
    AluRmRVex {
        size: OperandSize,
        op: AluRmROpcode,
        src1: Gpr,
        src2: GprMem,
        dst: WritableGpr,
    },
    AluConstOp {
        op: AluRmiROpcode,
        size: OperandSize,
        dst: WritableGpr,
    },
    UnaryRmR {
        size: OperandSize,
        op: UnaryRmROpcode,
        src: GprMem,
        dst: WritableGpr,
    },
    UnaryRmRVex {
        size: OperandSize,
        op: UnaryRmRVexOpcode,
        src: GprMem,
        dst: WritableGpr,
    },
    UnaryRmRImmVex {
        size: OperandSize,
        op: UnaryRmRImmVexOpcode,
        src: GprMem,
        dst: WritableGpr,
        imm: u8,
    },
    Not {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Neg {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Div {
        size: OperandSize,
        sign: DivSignedness,
        trap: TrapCode,
        divisor: GprMem,
        dividend_lo: Gpr,
        dividend_hi: Gpr,
        dst_quotient: WritableGpr,
        dst_remainder: WritableGpr,
    },
    Div8 {
        sign: DivSignedness,
        trap: TrapCode,
        divisor: GprMem,
        dividend: Gpr,
        dst: WritableGpr,
    },
    Mul {
        size: OperandSize,
        signed: bool,
        src1: Gpr,
        src2: GprMem,
        dst_lo: WritableGpr,
        dst_hi: WritableGpr,
    },
    Mul8 {
        signed: bool,
        src1: Gpr,
        src2: GprMem,
        dst: WritableGpr,
    },
    IMul {
        size: OperandSize,
        src1: Gpr,
        src2: GprMem,
        dst: WritableGpr,
    },
    IMulImm {
        size: OperandSize,
        src1: GprMem,
        src2: i32,
        dst: WritableGpr,
    },
    CheckedSRemSeq {
        size: OperandSize,
        dividend_lo: Gpr,
        dividend_hi: Gpr,
        divisor: Gpr,
        dst_quotient: WritableGpr,
        dst_remainder: WritableGpr,
    },
    CheckedSRemSeq8 {
        dividend: Gpr,
        divisor: Gpr,
        dst: WritableGpr,
    },
    SignExtendData {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Imm {
        dst_size: OperandSize,
        simm64: u64,
        dst: WritableGpr,
    },
    MovRR {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    MovFromPReg {
        src: PReg,
        dst: WritableGpr,
    },
    MovToPReg {
        src: Gpr,
        dst: PReg,
    },
    MovzxRmR {
        ext_mode: ExtMode,
        src: GprMem,
        dst: WritableGpr,
    },
    Mov64MR {
        src: SyntheticAmode,
        dst: WritableGpr,
    },
    LoadEffectiveAddress {
        addr: SyntheticAmode,
        dst: WritableGpr,
        size: OperandSize,
    },
    MovsxRmR {
        ext_mode: ExtMode,
        src: GprMem,
        dst: WritableGpr,
    },
    MovImmM {
        size: OperandSize,
        simm32: i32,
        dst: SyntheticAmode,
    },
    MovRM {
        size: OperandSize,
        src: Gpr,
        dst: SyntheticAmode,
    },
    ShiftR {
        size: OperandSize,
        kind: ShiftKind,
        src: Gpr,
        num_bits: Imm8Gpr,
        dst: WritableGpr,
    },
    XmmRmiReg {
        opcode: SseOpcode,
        src1: Xmm,
        src2: XmmMemAlignedImm,
        dst: WritableXmm,
    },
    CmpRmiR {
        size: OperandSize,
        opcode: CmpOpcode,
        src1: Gpr,
        src2: GprMemImm,
    },
    Setcc {
        cc: CC,
        dst: WritableGpr,
    },
    Bswap {
        size: OperandSize,
        src: Gpr,
        dst: WritableGpr,
    },
    Cmove {
        size: OperandSize,
        cc: CC,
        consequent: GprMem,
        alternative: Gpr,
        dst: WritableGpr,
    },
    XmmCmove {
        ty: Type,
        cc: CC,
        consequent: Xmm,
        alternative: Xmm,
        dst: WritableXmm,
    },
    Push64 {
        src: GprMemImm,
    },
    Pop64 {
        dst: WritableGpr,
    },
    StackProbeLoop {
        tmp: Writable<Reg>,
        frame_size: u32,
        guard_size: u32,
    },
    XmmRmR {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMemAligned,
        dst: WritableXmm,
    },
    XmmRmRUnaligned {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMem,
        dst: WritableXmm,
    },
    XmmRmRBlend {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMemAligned,
        mask: Xmm,
        dst: WritableXmm,
    },
    XmmRmiRVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMemImm,
        dst: WritableXmm,
    },
    XmmRmRImmVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmVexPinsr {
        op: AvxOpcode,
        src1: Xmm,
        src2: GprMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmRmRVex3 {
        op: AvxOpcode,
        src1: Xmm,
        src2: Xmm,
        src3: XmmMem,
        dst: WritableXmm,
    },
    XmmRmRBlendVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMem,
        mask: Xmm,
        dst: WritableXmm,
    },
    XmmUnaryRmRVex {
        op: AvxOpcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmRImmVex {
        op: AvxOpcode,
        src: XmmMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmMovRMVex {
        op: AvxOpcode,
        src: Xmm,
        dst: SyntheticAmode,
    },
    XmmMovRMImmVex {
        op: AvxOpcode,
        src: Xmm,
        dst: SyntheticAmode,
        imm: u8,
    },
    XmmToGprImmVex {
        op: AvxOpcode,
        src: Xmm,
        dst: WritableGpr,
        imm: u8,
    },
    GprToXmmVex {
        op: AvxOpcode,
        src: GprMem,
        dst: WritableXmm,
        src_size: OperandSize,
    },
    XmmToGprVex {
        op: AvxOpcode,
        src: Xmm,
        dst: WritableGpr,
        dst_size: OperandSize,
    },
    XmmCmpRmRVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: XmmMem,
    },
    XmmRmREvex {
        op: Avx512Opcode,
        src1: Xmm,
        src2: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmRImmEvex {
        op: Avx512Opcode,
        src: XmmMem,
        dst: WritableXmm,
        imm: u8,
    },
    XmmRmREvex3 {
        op: Avx512Opcode,
        src1: Xmm,
        src2: Xmm,
        src3: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmR {
        op: SseOpcode,
        src: XmmMemAligned,
        dst: WritableXmm,
    },
    XmmUnaryRmRUnaligned {
        op: SseOpcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmUnaryRmRImm {
        op: SseOpcode,
        src: XmmMemAligned,
        imm: u8,
        dst: WritableXmm,
    },
    XmmUnaryRmREvex {
        op: Avx512Opcode,
        src: XmmMem,
        dst: WritableXmm,
    },
    XmmMovRM {
        op: SseOpcode,
        src: Xmm,
        dst: SyntheticAmode,
    },
    XmmMovRMImm {
        op: SseOpcode,
        src: Xmm,
        dst: SyntheticAmode,
        imm: u8,
    },
    XmmToGpr {
        op: SseOpcode,
        src: Xmm,
        dst: WritableGpr,
        dst_size: OperandSize,
    },
    XmmToGprImm {
        op: SseOpcode,
        src: Xmm,
        dst: WritableGpr,
        imm: u8,
    },
    GprToXmm {
        op: SseOpcode,
        src: GprMem,
        dst: WritableXmm,
        src_size: OperandSize,
    },
    CvtIntToFloat {
        op: SseOpcode,
        src1: Xmm,
        src2: GprMem,
        dst: WritableXmm,
        src2_size: OperandSize,
    },
    CvtIntToFloatVex {
        op: AvxOpcode,
        src1: Xmm,
        src2: GprMem,
        dst: WritableXmm,
        src2_size: OperandSize,
    },
    CvtUint64ToFloatSeq {
        dst_size: OperandSize,
        src: Gpr,
        dst: WritableXmm,
        tmp_gpr1: WritableGpr,
        tmp_gpr2: WritableGpr,
    },
    CvtFloatToSintSeq {
        dst_size: OperandSize,
        src_size: OperandSize,
        is_saturating: bool,
        src: Xmm,
        dst: WritableGpr,
        tmp_gpr: WritableGpr,
        tmp_xmm: WritableXmm,
    },
    CvtFloatToUintSeq {
        dst_size: OperandSize,
        src_size: OperandSize,
        is_saturating: bool,
        src: Xmm,
        dst: WritableGpr,
        tmp_gpr: WritableGpr,
        tmp_xmm: WritableXmm,
        tmp_xmm2: WritableXmm,
    },
    XmmMinMaxSeq {
        size: OperandSize,
        is_min: bool,
        lhs: Xmm,
        rhs: Xmm,
        dst: WritableXmm,
    },
    XmmCmpRmR {
        op: SseOpcode,
        src1: Xmm,
        src2: XmmMemAligned,
    },
    XmmRmRImm {
        op: SseOpcode,
        src1: Reg,
        src2: RegMem,
        dst: Writable<Reg>,
        imm: u8,
        size: OperandSize,
    },
    CallKnown {
        dest: ExternalName,
        opcode: Opcode,
        info: Option<Box<CallInfo>>,
    },
    CallUnknown {
        dest: RegMem,
        opcode: Opcode,
        info: Option<Box<CallInfo>>,
    },
    ReturnCallKnown {
        callee: ExternalName,
        info: Box<ReturnCallInfo>,
    },
    ReturnCallUnknown {
        callee: Reg,
        info: Box<ReturnCallInfo>,
    },
    Args {
        args: Vec<ArgPair>,
    },
    Rets {
        rets: Vec<RetPair>,
    },
    Ret {
        stack_bytes_to_pop: u32,
    },
    JmpKnown {
        dst: MachLabel,
    },
    JmpIf {
        cc: CC,
        taken: MachLabel,
    },
    JmpCond {
        cc: CC,
        taken: MachLabel,
        not_taken: MachLabel,
    },
    JmpTableSeq {
        idx: Reg,
        tmp1: Writable<Reg>,
        tmp2: Writable<Reg>,
        default_target: MachLabel,
        targets: Box<Vec<MachLabel>>,
    },
    JmpUnknown {
        target: RegMem,
    },
    TrapIf {
        cc: CC,
        trap_code: TrapCode,
    },
    TrapIfAnd {
        cc1: CC,
        cc2: CC,
        trap_code: TrapCode,
    },
    TrapIfOr {
        cc1: CC,
        cc2: CC,
        trap_code: TrapCode,
    },
    Hlt,
    Ud2 {
        trap_code: TrapCode,
    },
    LoadExtName {
        dst: Writable<Reg>,
        name: Box<ExternalName>,
        offset: i64,
        distance: RelocDistance,
    },
    LockCmpxchg {
        ty: Type,
        replacement: Reg,
        expected: Reg,
        mem: SyntheticAmode,
        dst_old: Writable<Reg>,
    },
    AtomicRmwSeq {
        ty: Type,
        op: MachAtomicRmwOp,
        mem: SyntheticAmode,
        operand: Reg,
        temp: Writable<Reg>,
        dst_old: Writable<Reg>,
    },
    Fence {
        kind: FenceKind,
    },
    VirtualSPOffsetAdj {
        offset: i64,
    },
    XmmUninitializedValue {
        dst: WritableXmm,
    },
    ElfTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
    },
    MachOTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
    },
    CoffTlsGetAddr {
        symbol: ExternalName,
        dst: WritableGpr,
        tmp: WritableGpr,
    },
    Unwind {
        inst: UnwindInst,
    },
    DummyUse {
        reg: Reg,
    },

}
Expand description

Internal type MInst: defined at src/isa/x64/inst.isle line 8.

Variants§

§

Nop

Fields

§len: u8
§

AluRmiR

§

AluRM

§

AluRmRVex

§

AluConstOp

§

UnaryRmR

§

UnaryRmRVex

§

UnaryRmRImmVex

§

Not

Fields

§size: OperandSize
§src: Gpr
§dst: WritableGpr
§

Neg

Fields

§size: OperandSize
§src: Gpr
§dst: WritableGpr
§

Div

Fields

§size: OperandSize
§sign: DivSignedness
§trap: TrapCode
§divisor: GprMem
§dividend_lo: Gpr
§dividend_hi: Gpr
§dst_quotient: WritableGpr
§dst_remainder: WritableGpr
§

Div8

Fields

§sign: DivSignedness
§trap: TrapCode
§divisor: GprMem
§dividend: Gpr
§dst: WritableGpr
§

Mul

Fields

§size: OperandSize
§signed: bool
§src1: Gpr
§src2: GprMem
§dst_lo: WritableGpr
§dst_hi: WritableGpr
§

Mul8

Fields

§signed: bool
§src1: Gpr
§src2: GprMem
§dst: WritableGpr
§

IMul

Fields

§size: OperandSize
§src1: Gpr
§src2: GprMem
§dst: WritableGpr
§

IMulImm

Fields

§size: OperandSize
§src1: GprMem
§src2: i32
§dst: WritableGpr
§

CheckedSRemSeq

Fields

§size: OperandSize
§dividend_lo: Gpr
§dividend_hi: Gpr
§divisor: Gpr
§dst_quotient: WritableGpr
§dst_remainder: WritableGpr
§

CheckedSRemSeq8

Fields

§dividend: Gpr
§divisor: Gpr
§dst: WritableGpr
§

SignExtendData

Fields

§size: OperandSize
§src: Gpr
§dst: WritableGpr
§

Imm

Fields

§dst_size: OperandSize
§simm64: u64
§dst: WritableGpr
§

MovRR

Fields

§size: OperandSize
§src: Gpr
§dst: WritableGpr
§

MovFromPReg

Fields

§src: PReg
§dst: WritableGpr
§

MovToPReg

Fields

§src: Gpr
§dst: PReg
§

MovzxRmR

Fields

§ext_mode: ExtMode
§src: GprMem
§dst: WritableGpr
§

Mov64MR

§

LoadEffectiveAddress

§

MovsxRmR

Fields

§ext_mode: ExtMode
§src: GprMem
§dst: WritableGpr
§

MovImmM

Fields

§size: OperandSize
§simm32: i32
§dst: SyntheticAmode
§

MovRM

§

ShiftR

Fields

§size: OperandSize
§kind: ShiftKind
§src: Gpr
§num_bits: Imm8Gpr
§dst: WritableGpr
§

XmmRmiReg

§

CmpRmiR

Fields

§size: OperandSize
§opcode: CmpOpcode
§src1: Gpr
§src2: GprMemImm
§

Setcc

Fields

§cc: CC
§dst: WritableGpr
§

Bswap

Fields

§size: OperandSize
§src: Gpr
§dst: WritableGpr
§

Cmove

Fields

§size: OperandSize
§cc: CC
§consequent: GprMem
§alternative: Gpr
§dst: WritableGpr
§

XmmCmove

Fields

§ty: Type
§cc: CC
§consequent: Xmm
§alternative: Xmm
§dst: WritableXmm
§

Push64

Fields

§src: GprMemImm
§

Pop64

Fields

§dst: WritableGpr
§

StackProbeLoop

Fields

§tmp: Writable<Reg>
§frame_size: u32
§guard_size: u32
§

XmmRmR

§

XmmRmRUnaligned

Fields

§op: SseOpcode
§src1: Xmm
§src2: XmmMem
§dst: WritableXmm
§

XmmRmRBlend

Fields

§op: SseOpcode
§src1: Xmm
§src2: XmmMemAligned
§mask: Xmm
§dst: WritableXmm
§

XmmRmiRVex

Fields

§op: AvxOpcode
§src1: Xmm
§src2: XmmMemImm
§dst: WritableXmm
§

XmmRmRImmVex

Fields

§op: AvxOpcode
§src1: Xmm
§src2: XmmMem
§dst: WritableXmm
§imm: u8
§

XmmVexPinsr

Fields

§op: AvxOpcode
§src1: Xmm
§src2: GprMem
§dst: WritableXmm
§imm: u8
§

XmmRmRVex3

Fields

§op: AvxOpcode
§src1: Xmm
§src2: Xmm
§src3: XmmMem
§dst: WritableXmm
§

XmmRmRBlendVex

Fields

§op: AvxOpcode
§src1: Xmm
§src2: XmmMem
§mask: Xmm
§dst: WritableXmm
§

XmmUnaryRmRVex

§

XmmUnaryRmRImmVex

Fields

§op: AvxOpcode
§src: XmmMem
§dst: WritableXmm
§imm: u8
§

XmmMovRMVex

§

XmmMovRMImmVex

Fields

§op: AvxOpcode
§src: Xmm
§dst: SyntheticAmode
§imm: u8
§

XmmToGprImmVex

Fields

§op: AvxOpcode
§src: Xmm
§dst: WritableGpr
§imm: u8
§

GprToXmmVex

Fields

§op: AvxOpcode
§src: GprMem
§dst: WritableXmm
§src_size: OperandSize
§

XmmToGprVex

Fields

§op: AvxOpcode
§src: Xmm
§dst: WritableGpr
§dst_size: OperandSize
§

XmmCmpRmRVex

Fields

§op: AvxOpcode
§src1: Xmm
§src2: XmmMem
§

XmmRmREvex

Fields

§op: Avx512Opcode
§src1: Xmm
§src2: XmmMem
§dst: WritableXmm
§

XmmUnaryRmRImmEvex

§

XmmRmREvex3

Fields

§op: Avx512Opcode
§src1: Xmm
§src2: Xmm
§src3: XmmMem
§dst: WritableXmm
§

XmmUnaryRmR

§

XmmUnaryRmRUnaligned

§

XmmUnaryRmRImm

§

XmmUnaryRmREvex

§

XmmMovRM

§

XmmMovRMImm

Fields

§op: SseOpcode
§src: Xmm
§dst: SyntheticAmode
§imm: u8
§

XmmToGpr

Fields

§op: SseOpcode
§src: Xmm
§dst: WritableGpr
§dst_size: OperandSize
§

XmmToGprImm

Fields

§op: SseOpcode
§src: Xmm
§dst: WritableGpr
§imm: u8
§

GprToXmm

Fields

§op: SseOpcode
§src: GprMem
§dst: WritableXmm
§src_size: OperandSize
§

CvtIntToFloat

Fields

§op: SseOpcode
§src1: Xmm
§src2: GprMem
§dst: WritableXmm
§src2_size: OperandSize
§

CvtIntToFloatVex

Fields

§op: AvxOpcode
§src1: Xmm
§src2: GprMem
§dst: WritableXmm
§src2_size: OperandSize
§

CvtUint64ToFloatSeq

Fields

§dst_size: OperandSize
§src: Gpr
§dst: WritableXmm
§tmp_gpr1: WritableGpr
§tmp_gpr2: WritableGpr
§

CvtFloatToSintSeq

Fields

§dst_size: OperandSize
§src_size: OperandSize
§is_saturating: bool
§src: Xmm
§dst: WritableGpr
§tmp_gpr: WritableGpr
§tmp_xmm: WritableXmm
§

CvtFloatToUintSeq

Fields

§dst_size: OperandSize
§src_size: OperandSize
§is_saturating: bool
§src: Xmm
§dst: WritableGpr
§tmp_gpr: WritableGpr
§tmp_xmm: WritableXmm
§tmp_xmm2: WritableXmm
§

XmmMinMaxSeq

Fields

§size: OperandSize
§is_min: bool
§lhs: Xmm
§rhs: Xmm
§dst: WritableXmm
§

XmmCmpRmR

Fields

§op: SseOpcode
§src1: Xmm
§src2: XmmMemAligned
§

XmmRmRImm

Fields

§op: SseOpcode
§src1: Reg
§src2: RegMem
§dst: Writable<Reg>
§imm: u8
§size: OperandSize
§

CallKnown

Fields

§dest: ExternalName
§opcode: Opcode
§info: Option<Box<CallInfo>>
§

CallUnknown

Fields

§dest: RegMem
§opcode: Opcode
§info: Option<Box<CallInfo>>
§

ReturnCallKnown

Fields

§callee: ExternalName
§info: Box<ReturnCallInfo>
§

ReturnCallUnknown

Fields

§callee: Reg
§info: Box<ReturnCallInfo>
§

Args

Fields

§args: Vec<ArgPair>
§

Rets

Fields

§rets: Vec<RetPair>
§

Ret

Fields

§stack_bytes_to_pop: u32
§

JmpKnown

Fields

§dst: MachLabel
§

JmpIf

Fields

§cc: CC
§taken: MachLabel
§

JmpCond

Fields

§cc: CC
§taken: MachLabel
§not_taken: MachLabel
§

JmpTableSeq

Fields

§idx: Reg
§tmp1: Writable<Reg>
§tmp2: Writable<Reg>
§default_target: MachLabel
§targets: Box<Vec<MachLabel>>
§

JmpUnknown

Fields

§target: RegMem
§

TrapIf

Fields

§cc: CC
§trap_code: TrapCode
§

TrapIfAnd

Fields

§cc1: CC
§cc2: CC
§trap_code: TrapCode
§

TrapIfOr

Fields

§cc1: CC
§cc2: CC
§trap_code: TrapCode
§

Hlt

§

Ud2

Fields

§trap_code: TrapCode
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LoadExtName

Fields

§dst: Writable<Reg>
§name: Box<ExternalName>
§offset: i64
§distance: RelocDistance
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LockCmpxchg

Fields

§ty: Type
§replacement: Reg
§expected: Reg
§mem: SyntheticAmode
§dst_old: Writable<Reg>
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AtomicRmwSeq

Fields

§ty: Type
§op: MachAtomicRmwOp
§mem: SyntheticAmode
§operand: Reg
§temp: Writable<Reg>
§dst_old: Writable<Reg>
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Fence

Fields

§kind: FenceKind
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VirtualSPOffsetAdj

Fields

§offset: i64
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XmmUninitializedValue

Fields

§dst: WritableXmm
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ElfTlsGetAddr

Fields

§symbol: ExternalName
§dst: WritableGpr
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MachOTlsGetAddr

Fields

§symbol: ExternalName
§dst: WritableGpr
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CoffTlsGetAddr

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Unwind

Fields

§inst: UnwindInst
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DummyUse

Fields

§reg: Reg

Trait Implementations§

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impl Clone for MInst

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fn clone(&self) -> MInst

Returns a copy of the value. Read more
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fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for Inst

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fn fmt(&self, fmt: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl MachInst for Inst

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type ABIMachineSpec = X64ABIMachineSpec

The ABI machine spec for this MachInst.
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fn get_operands(&mut self, collector: &mut impl OperandVisitor)

Return the registers referenced by this machine instruction along with the modes of reference (use, def, modify).
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fn is_move(&self) -> Option<(Writable<Reg>, Reg)>

If this is a simple move, return the (source, destination) tuple of registers.
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fn is_included_in_clobbers(&self) -> bool

Should this instruction be included in the clobber-set?
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fn is_trap(&self) -> bool

Is this an unconditional trap?
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fn is_args(&self) -> bool

Is this an “args” pseudoinst?
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fn is_term(&self) -> MachTerminator

Is this a terminator (branch or ret)? If so, return its type (ret/uncond/cond) and target if applicable.
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fn is_mem_access(&self) -> bool

Does this instruction access memory?
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fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, ty: Type) -> Inst

Generate a move.
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fn gen_nop(preferred_size: usize) -> Inst

Generate a NOP. The preferred_size parameter allows the caller to request a NOP of that size, or as close to it as possible. The machine backend may return a NOP whose binary encoding is smaller than the preferred size, but must not return a NOP that is larger. However, the instruction must have a nonzero size if preferred_size is nonzero.
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fn rc_for_type( ty: Type ) -> CodegenResult<(&'static [RegClass], &'static [Type])>

Determine register class(es) to store the given Cranelift type, and the Cranelift type actually stored in the underlying register(s). May return an error if the type isn’t supported by this backend. Read more
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fn canonical_type_for_rc(rc: RegClass) -> Type

Get an appropriate type that can fully hold a value in a given register class. This may not be the only type that maps to that class, but when used with gen_move() or the ABI trait’s load/spill constructors, it should produce instruction(s) that move the entire register contents.
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fn gen_jump(label: MachLabel) -> Inst

Generate a jump to another target. Used during lowering of control flow.
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fn gen_imm_u64(value: u64, dst: Writable<Reg>) -> Option<Self>

Generate a store of an immediate 64-bit integer to a register. Used by the control plane to generate random instructions.
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fn gen_imm_f64( value: f64, tmp: Writable<Reg>, dst: Writable<Reg> ) -> SmallVec<[Self; 2]>

Generate a store of an immediate 64-bit integer to a register. Used by the control plane to generate random instructions. The tmp register may be used by architectures which don’t support writing immediate values to floating point registers directly.
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fn gen_dummy_use(reg: Reg) -> Self

Generate a dummy instruction that will keep a value alive but has no other purpose.
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fn worst_case_size() -> CodeOffset

What is the worst-case instruction size emitted by this instruction type?
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fn ref_type_regclass(_: &Flags) -> RegClass

What is the register class used for reference types (GC-observable pointers)? Can be dependent on compilation flags.
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fn is_safepoint(&self) -> bool

Is this a safepoint?
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fn function_alignment() -> FunctionAlignment

Returns a description of the alignment required for functions for this architecture.
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type LabelUse = LabelUse

A label-use kind: a type that describes the types of label references that can occur in an instruction.
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const TRAP_OPCODE: &'static [u8] = _

Byte representation of a trap opcode which is inserted by MachBuffer during its defer_trap method.
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fn align_basic_block(offset: CodeOffset) -> CodeOffset

Align a basic block offset (from start of function). By default, no alignment occurs.
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fn gen_block_start( _is_indirect_branch_target: bool, _is_forward_edge_cfi_enabled: bool ) -> Option<Self>

Generate an instruction that must appear at the beginning of a basic block, if any. Note that the return value must not be subject to register allocation.
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impl MachInstEmit for Inst

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type State = EmitState

Persistent state carried across emit invocations.
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type Info = EmitInfo

Constant information used in emit invocations.
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fn emit( &self, allocs: &[Allocation], sink: &mut MachBuffer<Inst>, info: &Self::Info, state: &mut Self::State )

Emit the instruction.
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fn pretty_print_inst( &self, allocs: &[Allocation], _: &mut Self::State ) -> String

Pretty-print the instruction.
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impl MachInstEmitState<MInst> for EmitState

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fn new(abi: &Callee<X64ABIMachineSpec>, ctrl_plane: ControlPlane) -> Self

Create a new emission state given the ABI object.
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fn pre_safepoint(&mut self, stack_map: StackMap)

Update the emission state before emitting an instruction that is a safepoint.
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fn ctrl_plane_mut(&mut self) -> &mut ControlPlane

The emission state holds ownership of a control plane, so it doesn’t have to be passed around explicitly too much. ctrl_plane_mut may be used if temporary access to the control plane is needed by some other function that doesn’t have access to the emission state.
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fn take_ctrl_plane(self) -> ControlPlane

Used to continue using a control plane after the emission state is not needed anymore.
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fn on_new_block(&mut self)

A hook that triggers when first emitting a new block. It is guaranteed to be called before any instructions are emitted.

Auto Trait Implementations§

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impl Freeze for MInst

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impl RefUnwindSafe for MInst

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impl Send for MInst

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impl Sync for MInst

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impl Unpin for MInst

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impl UnwindSafe for MInst

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> Same for T

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type Output = T

Should always be Self
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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

The resulting type after obtaining ownership.
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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.