Module cranelift_codegen::isa::aarch64::inst::args

AArch64 ISA definitions: instruction arguments.

Structs

• ShiftOpAndAmt
  A shift operator with an amount, guaranteed to be within range.
• ShiftOpShiftImm
  A shift operator amount.

Enums

• BranchTarget
  A branch target. Either unresolved (basic-block index) or resolved (offset from end of current instruction).
• Cond
  Condition for conditional branches.
• CondBrKind
  The kind of conditional branch: the common-case-optimized “reg-is-zero” / “reg-is-nonzero” variants, or the generic one that tests the machine condition codes.
• ExtendOp
  An extend operator for a register.
• MemLabel
  A reference to some memory address.
• OperandSize
  Type used to communicate the operand size of a machine instruction, as AArch64 has 32- and 64-bit variants of many instructions (and integer registers).
• PairAMode
  Internal type PairAMode: defined at src/isa/aarch64/inst.isle line 1197.
• ScalarSize
  Type used to communicate the size of a scalar SIMD & FP operand.
• ShiftOp
  A shift operator for a register or immediate.
• TestBitAndBranchKind
  Internal type TestBitAndBranchKind: defined at src/isa/aarch64/inst.isle line 1217.
• VectorSize
  Type used to communicate the size of a vector operand.