Enum Opcode

#[repr(u8)]
pub enum Opcode {
    Ret = 0,
    Call = 1,
    Call1 = 2,
    Call2 = 3,
    Call3 = 4,
    Call4 = 5,
    CallIndirect = 6,
    Jump = 7,
    XJump = 8,
    BrIf = 9,
    BrIfNot = 10,
    BrIfXeq32 = 11,
    BrIfXneq32 = 12,
    BrIfXslt32 = 13,
    BrIfXslteq32 = 14,
    BrIfXult32 = 15,
    BrIfXulteq32 = 16,
    BrIfXeq64 = 17,
    BrIfXneq64 = 18,
    BrIfXslt64 = 19,
    BrIfXslteq64 = 20,
    BrIfXult64 = 21,
    BrIfXulteq64 = 22,
    BrIfXeq32I8 = 23,
    BrIfXeq32I32 = 24,
    BrIfXneq32I8 = 25,
    BrIfXneq32I32 = 26,
    BrIfXslt32I8 = 27,
    BrIfXslt32I32 = 28,
    BrIfXsgt32I8 = 29,
    BrIfXsgt32I32 = 30,
    BrIfXslteq32I8 = 31,
    BrIfXslteq32I32 = 32,
    BrIfXsgteq32I8 = 33,
    BrIfXsgteq32I32 = 34,
    BrIfXult32U8 = 35,
    BrIfXult32U32 = 36,
    BrIfXulteq32U8 = 37,
    BrIfXulteq32U32 = 38,
    BrIfXugt32U8 = 39,
    BrIfXugt32U32 = 40,
    BrIfXugteq32U8 = 41,
    BrIfXugteq32U32 = 42,
    BrIfXeq64I8 = 43,
    BrIfXeq64I32 = 44,
    BrIfXneq64I8 = 45,
    BrIfXneq64I32 = 46,
    BrIfXslt64I8 = 47,
    BrIfXslt64I32 = 48,
    BrIfXsgt64I8 = 49,
    BrIfXsgt64I32 = 50,
    BrIfXslteq64I8 = 51,
    BrIfXslteq64I32 = 52,
    BrIfXsgteq64I8 = 53,
    BrIfXsgteq64I32 = 54,
    BrIfXult64U8 = 55,
    BrIfXult64U32 = 56,
    BrIfXulteq64U8 = 57,
    BrIfXulteq64U32 = 58,
    BrIfXugt64U8 = 59,
    BrIfXugt64U32 = 60,
    BrIfXugteq64U8 = 61,
    BrIfXugteq64U32 = 62,
    BrTable32 = 63,
    Xmov = 64,
    Xzero = 65,
    Xone = 66,
    Xconst8 = 67,
    Xconst16 = 68,
    Xconst32 = 69,
    Xconst64 = 70,
    Xadd32 = 71,
    Xadd32U8 = 72,
    Xadd32U32 = 73,
    Xadd64 = 74,
    Xadd64U8 = 75,
    Xadd64U32 = 76,
    Xmadd32 = 77,
    Xmadd64 = 78,
    Xsub32 = 79,
    Xsub32U8 = 80,
    Xsub32U32 = 81,
    Xsub64 = 82,
    Xsub64U8 = 83,
    Xsub64U32 = 84,
    XMul32 = 85,
    Xmul32S8 = 86,
    Xmul32S32 = 87,
    XMul64 = 88,
    Xmul64S8 = 89,
    Xmul64S32 = 90,
    Xctz32 = 91,
    Xctz64 = 92,
    Xclz32 = 93,
    Xclz64 = 94,
    Xpopcnt32 = 95,
    Xpopcnt64 = 96,
    Xrotl32 = 97,
    Xrotl64 = 98,
    Xrotr32 = 99,
    Xrotr64 = 100,
    Xshl32 = 101,
    Xshr32S = 102,
    Xshr32U = 103,
    Xshl64 = 104,
    Xshr64S = 105,
    Xshr64U = 106,
    Xshl32U6 = 107,
    Xshr32SU6 = 108,
    Xshr32UU6 = 109,
    Xshl64U6 = 110,
    Xshr64SU6 = 111,
    Xshr64UU6 = 112,
    Xneg32 = 113,
    Xneg64 = 114,
    Xeq64 = 115,
    Xneq64 = 116,
    Xslt64 = 117,
    Xslteq64 = 118,
    Xult64 = 119,
    Xulteq64 = 120,
    Xeq32 = 121,
    Xneq32 = 122,
    Xslt32 = 123,
    Xslteq32 = 124,
    Xult32 = 125,
    Xulteq32 = 126,
    XLoad8U32O32 = 127,
    XLoad8S32O32 = 128,
    XLoad16LeU32O32 = 129,
    XLoad16LeS32O32 = 130,
    XLoad32LeO32 = 131,
    XLoad64LeO32 = 132,
    XStore8O32 = 133,
    XStore16LeO32 = 134,
    XStore32LeO32 = 135,
    XStore64LeO32 = 136,
    XLoad8U32Z = 137,
    XLoad8S32Z = 138,
    XLoad16LeU32Z = 139,
    XLoad16LeS32Z = 140,
    XLoad32LeZ = 141,
    XLoad64LeZ = 142,
    XStore8Z = 143,
    XStore16LeZ = 144,
    XStore32LeZ = 145,
    XStore64LeZ = 146,
    XLoad8U32G32 = 147,
    XLoad8S32G32 = 148,
    XLoad16LeU32G32 = 149,
    XLoad16LeS32G32 = 150,
    XLoad32LeG32 = 151,
    XLoad64LeG32 = 152,
    XStore8G32 = 153,
    XStore16LeG32 = 154,
    XStore32LeG32 = 155,
    XStore64LeG32 = 156,
    XLoad8U32G32Bne = 157,
    XLoad8S32G32Bne = 158,
    XLoad16LeU32G32Bne = 159,
    XLoad16LeS32G32Bne = 160,
    XLoad32LeG32Bne = 161,
    XLoad64LeG32Bne = 162,
    XStore8G32Bne = 163,
    XStore16LeG32Bne = 164,
    XStore32LeG32Bne = 165,
    XStore64LeG32Bne = 166,
    PushFrame = 167,
    PopFrame = 168,
    PushFrameSave = 169,
    PopFrameRestore = 170,
    StackAlloc32 = 171,
    StackFree32 = 172,
    Zext8 = 173,
    Zext16 = 174,
    Zext32 = 175,
    Sext8 = 176,
    Sext16 = 177,
    Sext32 = 178,
    XAbs32 = 179,
    XAbs64 = 180,
    XDiv32S = 181,
    XDiv64S = 182,
    XDiv32U = 183,
    XDiv64U = 184,
    XRem32S = 185,
    XRem64S = 186,
    XRem32U = 187,
    XRem64U = 188,
    XBand32 = 189,
    Xband32S8 = 190,
    Xband32S32 = 191,
    XBand64 = 192,
    Xband64S8 = 193,
    Xband64S32 = 194,
    XBor32 = 195,
    Xbor32S8 = 196,
    Xbor32S32 = 197,
    XBor64 = 198,
    Xbor64S8 = 199,
    Xbor64S32 = 200,
    XBxor32 = 201,
    Xbxor32S8 = 202,
    Xbxor32S32 = 203,
    XBxor64 = 204,
    Xbxor64S8 = 205,
    Xbxor64S32 = 206,
    XBnot32 = 207,
    XBnot64 = 208,
    Xmin32U = 209,
    Xmin32S = 210,
    Xmax32U = 211,
    Xmax32S = 212,
    Xmin64U = 213,
    Xmin64S = 214,
    Xmax64U = 215,
    Xmax64S = 216,
    XSelect32 = 217,
    XSelect64 = 218,
    ExtendedOp = 219,
}

An opcode without its immediates and operands.

Variants

Ret = 0

Transfer control the address in the lr register.

Call = 1

Transfer control to the PC at the given offset and set the lr register to the PC just after this instruction.

This instruction generally assumes that the Pulley ABI is being respected where arguments are in argument registers (starting at x0 for integer arguments) and results are in result registers. This instruction itself assume that all arguments are already in their registers. Subsequent instructions below enable moving arguments into the correct registers as part of the same call instruction.

Call1 = 2

Like call, but also x0 = arg1

Call2 = 3

Like call, but also x0, x1 = arg1, arg2

Call3 = 4

Like call, but also x0, x1, x2 = arg1, arg2, arg3

Call4 = 5

Like call, but also x0, x1, x2, x3 = arg1, arg2, arg3, arg4

CallIndirect = 6

Transfer control to the PC in reg and set lr to the PC just after this instruction.

Jump = 7

Unconditionally transfer control to the PC at the given offset.

XJump = 8

Unconditionally transfer control to the PC at specified register.

BrIf = 9

Conditionally transfer control to the given PC offset if low32(cond) contains a non-zero value.

BrIfNot = 10

Conditionally transfer control to the given PC offset if low32(cond) contains a zero value.

BrIfXeq32 = 11

Branch if a == b.

BrIfXneq32 = 12

Branch if a != b.

BrIfXslt32 = 13

Branch if signed a < b.

BrIfXslteq32 = 14

Branch if signed a <= b.

BrIfXult32 = 15

Branch if unsigned a < b.

BrIfXulteq32 = 16

Branch if unsigned a <= b.

BrIfXeq64 = 17

Branch if a == b.

BrIfXneq64 = 18

Branch if a != b.

BrIfXslt64 = 19

Branch if signed a < b.

BrIfXslteq64 = 20

Branch if signed a <= b.

BrIfXult64 = 21

Branch if unsigned a < b.

BrIfXulteq64 = 22

Branch if unsigned a <= b.

BrIfXeq32I8 = 23

Branch if a == b.

BrIfXeq32I32 = 24

Branch if a == b.

BrIfXneq32I8 = 25

Branch if a != b.

BrIfXneq32I32 = 26

Branch if a != b.

BrIfXslt32I8 = 27

Branch if signed a < b.

BrIfXslt32I32 = 28

Branch if signed a < b.

BrIfXsgt32I8 = 29

Branch if signed a > b.

BrIfXsgt32I32 = 30

Branch if signed a > b.

BrIfXslteq32I8 = 31

Branch if signed a <= b.

BrIfXslteq32I32 = 32

Branch if signed a <= b.

BrIfXsgteq32I8 = 33

Branch if signed a >= b.

BrIfXsgteq32I32 = 34

Branch if signed a >= b.

BrIfXult32U8 = 35

Branch if unsigned a < b.

BrIfXult32U32 = 36

Branch if unsigned a < b.

BrIfXulteq32U8 = 37

Branch if unsigned a <= b.

BrIfXulteq32U32 = 38

Branch if unsigned a <= b.

BrIfXugt32U8 = 39

Branch if unsigned a > b.

BrIfXugt32U32 = 40

Branch if unsigned a > b.

BrIfXugteq32U8 = 41

Branch if unsigned a >= b.

BrIfXugteq32U32 = 42

Branch if unsigned a >= b.

BrIfXeq64I8 = 43

Branch if a == b.

BrIfXeq64I32 = 44

Branch if a == b.

BrIfXneq64I8 = 45

Branch if a != b.

BrIfXneq64I32 = 46

Branch if a != b.

BrIfXslt64I8 = 47

Branch if signed a < b.

BrIfXslt64I32 = 48

Branch if signed a < b.

BrIfXsgt64I8 = 49

Branch if signed a > b.

BrIfXsgt64I32 = 50

Branch if signed a > b.

BrIfXslteq64I8 = 51

Branch if signed a <= b.

BrIfXslteq64I32 = 52

Branch if signed a <= b.

BrIfXsgteq64I8 = 53

Branch if signed a >= b.

BrIfXsgteq64I32 = 54

Branch if signed a >= b.

BrIfXult64U8 = 55

Branch if unsigned a < b.

BrIfXult64U32 = 56

Branch if unsigned a < b.

BrIfXulteq64U8 = 57

Branch if unsigned a <= b.

BrIfXulteq64U32 = 58

Branch if unsigned a <= b.

BrIfXugt64U8 = 59

Branch if unsigned a > b.

BrIfXugt64U32 = 60

Branch if unsigned a > b.

BrIfXugteq64U8 = 61

Branch if unsigned a >= b.

BrIfXugteq64U32 = 62

Branch if unsigned a >= b.

BrTable32 = 63

Branch to the label indicated by low32(idx).

After this instruction are amt instances of PcRelOffset and the idx selects which one will be branched to. The value of idx is clamped to amt - 1 (e.g. the last offset is the “default” one.

Xmov = 64

Move between x registers.

Xzero = 65

Set dst = 0

Xone = 66

Set dst = 1

Xconst8 = 67

Set dst = sign_extend(imm8).

Xconst16 = 68

Set dst = sign_extend(imm16).

Xconst32 = 69

Set dst = sign_extend(imm32).

Xconst64 = 70

Set dst = imm64.

Xadd32 = 71

32-bit wrapping addition: low32(dst) = low32(src1) + low32(src2).

The upper 32-bits of dst are unmodified.

Xadd32U8 = 72

Same as xadd32 but src2 is a zero-extended 8-bit immediate.

Xadd32U32 = 73

Same as xadd32 but src2 is a 32-bit immediate.

Xadd64 = 74

64-bit wrapping addition: dst = src1 + src2.

Xadd64U8 = 75

Same as xadd64 but src2 is a zero-extended 8-bit immediate.

Xadd64U32 = 76

Same as xadd64 but src2 is a zero-extended 32-bit immediate.

Xmadd32 = 77

low32(dst) = low32(src1) * low32(src2) + low32(src3)

Xmadd64 = 78

dst = src1 * src2 + src3

Xsub32 = 79

32-bit wrapping subtraction: low32(dst) = low32(src1) - low32(src2).

The upper 32-bits of dst are unmodified.

Xsub32U8 = 80

Same as xsub32 but src2 is a zero-extended 8-bit immediate.

Xsub32U32 = 81

Same as xsub32 but src2 is a 32-bit immediate.

Xsub64 = 82

64-bit wrapping subtraction: dst = src1 - src2.

Xsub64U8 = 83

Same as xsub64 but src2 is a zero-extended 8-bit immediate.

Xsub64U32 = 84

Same as xsub64 but src2 is a zero-extended 32-bit immediate.

XMul32 = 85

low32(dst) = low32(src1) * low32(src2)

Xmul32S8 = 86

Same as xmul64 but src2 is a sign-extended 8-bit immediate.

Xmul32S32 = 87

Same as xmul32 but src2 is a sign-extended 32-bit immediate.

XMul64 = 88

dst = src1 * src2

Xmul64S8 = 89

Same as xmul64 but src2 is a sign-extended 8-bit immediate.

Xmul64S32 = 90

Same as xmul64 but src2 is a sign-extended 64-bit immediate.

Xctz32 = 91

low32(dst) = trailing_zeros(low32(src))

Xctz64 = 92

dst = trailing_zeros(src)

Xclz32 = 93

low32(dst) = leading_zeros(low32(src))

Xclz64 = 94

dst = leading_zeros(src)

Xpopcnt32 = 95

low32(dst) = count_ones(low32(src))

Xpopcnt64 = 96

dst = count_ones(src)

Xrotl32 = 97

low32(dst) = rotate_left(low32(src1), low32(src2))

Xrotl64 = 98

dst = rotate_left(src1, src2)

Xrotr32 = 99

low32(dst) = rotate_right(low32(src1), low32(src2))

Xrotr64 = 100

dst = rotate_right(src1, src2)

Xshl32 = 101

low32(dst) = low32(src1) << low5(src2)

Xshr32S = 102

low32(dst) = low32(src1) >> low5(src2)

Xshr32U = 103

low32(dst) = low32(src1) >> low5(src2)

Xshl64 = 104

dst = src1 << low5(src2)

Xshr64S = 105

dst = src1 >> low6(src2)

Xshr64U = 106

dst = src1 >> low6(src2)

Xshl32U6 = 107

low32(dst) = low32(src1) << low5(src2)

Xshr32SU6 = 108

low32(dst) = low32(src1) >> low5(src2)

Xshr32UU6 = 109

low32(dst) = low32(src1) >> low5(src2)

Xshl64U6 = 110

dst = src1 << low5(src2)

Xshr64SU6 = 111

dst = src1 >> low6(src2)

Xshr64UU6 = 112

dst = src1 >> low6(src2)

Xneg32 = 113

low32(dst) = -low32(src)

Xneg64 = 114

dst = -src

Xeq64 = 115

low32(dst) = src1 == src2

Xneq64 = 116

low32(dst) = src1 != src2

Xslt64 = 117

low32(dst) = src1 < src2 (signed)

Xslteq64 = 118

low32(dst) = src1 <= src2 (signed)

Xult64 = 119

low32(dst) = src1 < src2 (unsigned)

Xulteq64 = 120

low32(dst) = src1 <= src2 (unsigned)

Xeq32 = 121

low32(dst) = low32(src1) == low32(src2)

Xneq32 = 122

low32(dst) = low32(src1) != low32(src2)

Xslt32 = 123

low32(dst) = low32(src1) < low32(src2) (signed)

Xslteq32 = 124

low32(dst) = low32(src1) <= low32(src2) (signed)

Xult32 = 125

low32(dst) = low32(src1) < low32(src2) (unsigned)

Xulteq32 = 126

low32(dst) = low32(src1) <= low32(src2) (unsigned)

XLoad8U32O32 = 127

low32(dst) = zext_8_32(*addr)

XLoad8S32O32 = 128

low32(dst) = sext_8_32(*addr)

XLoad16LeU32O32 = 129

low32(dst) = o32ext_16_32(*addr)

XLoad16LeS32O32 = 130

low32(dst) = sext_16_32(*addr)

XLoad32LeO32 = 131

low32(dst) = *addr

XLoad64LeO32 = 132

dst = *addr

XStore8O32 = 133

*addr = low8(src)

XStore16LeO32 = 134

*addr = low16(src)

XStore32LeO32 = 135

*addr = low32(src)

XStore64LeO32 = 136

*addr = src

XLoad8U32Z = 137

low32(dst) = zext_8_32(*addr)

XLoad8S32Z = 138

low32(dst) = sext_8_32(*addr)

XLoad16LeU32Z = 139

low32(dst) = zext_16_32(*addr)

XLoad16LeS32Z = 140

low32(dst) = sext_16_32(*addr)

XLoad32LeZ = 141

low32(dst) = *addr

XLoad64LeZ = 142

dst = *addr

XStore8Z = 143

*addr = low8(src)

XStore16LeZ = 144

*addr = low16(src)

XStore32LeZ = 145

*addr = low32(src)

XStore64LeZ = 146

*addr = src

XLoad8U32G32 = 147

low32(dst) = zext_8_32(*addr)

XLoad8S32G32 = 148

low32(dst) = sext_8_32(*addr)

XLoad16LeU32G32 = 149

low32(dst) = zext_16_32(*addr)

XLoad16LeS32G32 = 150

low32(dst) = sext_16_32(*addr)

XLoad32LeG32 = 151

low32(dst) = *addr

XLoad64LeG32 = 152

dst = *addr

XStore8G32 = 153

*addr = low8(src)

XStore16LeG32 = 154

*addr = low16(src)

XStore32LeG32 = 155

*addr = low32(src)

XStore64LeG32 = 156

*addr = src

XLoad8U32G32Bne = 157

low32(dst) = zext_8_32(*addr)

XLoad8S32G32Bne = 158

low32(dst) = sext_8_32(*addr)

XLoad16LeU32G32Bne = 159

low32(dst) = zext_16_32(*addr)

XLoad16LeS32G32Bne = 160

low32(dst) = sext_16_32(*addr)

XLoad32LeG32Bne = 161

low32(dst) = *addr

XLoad64LeG32Bne = 162

dst = *addr

XStore8G32Bne = 163

*addr = low8(src)

XStore16LeG32Bne = 164

*addr = low16(src)

XStore32LeG32Bne = 165

*addr = low32(src)

XStore64LeG32Bne = 166

*addr = src

PushFrame = 167

push lr; push fp; fp = sp

PopFrame = 168

sp = fp; pop fp; pop lr

PushFrameSave = 169

Macro-instruction to enter a function, allocate some stack, and then save some registers.

This is equivalent to push_frame, stack_alloc32 amt, then saving all of regs to the top of the stack just allocated.

PopFrameRestore = 170

Inverse of push_frame_save. Restores regs from the top of the stack, then runs stack_free32 amt, then runs pop_frame.

StackAlloc32 = 171

sp = sp.checked_sub(amt)

StackFree32 = 172

sp = sp + amt

Zext8 = 173

dst = zext(low8(src))

Zext16 = 174

dst = zext(low16(src))

Zext32 = 175

dst = zext(low32(src))

Sext8 = 176

dst = sext(low8(src))

Sext16 = 177

dst = sext(low16(src))

Sext32 = 178

dst = sext(low32(src))

XAbs32 = 179

low32(dst) = |low32(src)|

XAbs64 = 180

dst = |src|

XDiv32S = 181

low32(dst) = low32(src1) / low32(src2) (signed)

XDiv64S = 182

dst = src1 / src2 (signed)

XDiv32U = 183

low32(dst) = low32(src1) / low32(src2) (unsigned)

XDiv64U = 184

dst = src1 / src2 (unsigned)

XRem32S = 185

low32(dst) = low32(src1) % low32(src2) (signed)

XRem64S = 186

dst = src1 / src2 (signed)

XRem32U = 187

low32(dst) = low32(src1) % low32(src2) (unsigned)

XRem64U = 188

dst = src1 / src2 (unsigned)

XBand32 = 189

low32(dst) = low32(src1) & low32(src2)

Xband32S8 = 190

Same as xband64 but src2 is a sign-extended 8-bit immediate.

Xband32S32 = 191

Same as xband32 but src2 is a sign-extended 32-bit immediate.

XBand64 = 192

dst = src1 & src2

Xband64S8 = 193

Same as xband64 but src2 is a sign-extended 8-bit immediate.

Xband64S32 = 194

Same as xband64 but src2 is a sign-extended 32-bit immediate.

XBor32 = 195

low32(dst) = low32(src1) | low32(src2)

Xbor32S8 = 196

Same as xbor64 but src2 is a sign-extended 8-bit immediate.

Xbor32S32 = 197

Same as xbor32 but src2 is a sign-extended 32-bit immediate.

XBor64 = 198

dst = src1 | src2

Xbor64S8 = 199

Same as xbor64 but src2 is a sign-extended 8-bit immediate.

Xbor64S32 = 200

Same as xbor64 but src2 is a sign-extended 32-bit immediate.

XBxor32 = 201

low32(dst) = low32(src1) ^ low32(src2)

Xbxor32S8 = 202

Same as xbxor64 but src2 is a sign-extended 8-bit immediate.

Xbxor32S32 = 203

Same as xbxor32 but src2 is a sign-extended 32-bit immediate.

XBxor64 = 204

dst = src1 ^ src2

Xbxor64S8 = 205

Same as xbxor64 but src2 is a sign-extended 8-bit immediate.

Xbxor64S32 = 206

Same as xbxor64 but src2 is a sign-extended 32-bit immediate.

XBnot32 = 207

low32(dst) = !low32(src1)

XBnot64 = 208

dst = !src1

Xmin32U = 209

low32(dst) = min(low32(src1), low32(src2)) (unsigned)

Xmin32S = 210

low32(dst) = min(low32(src1), low32(src2)) (signed)

Xmax32U = 211

low32(dst) = max(low32(src1), low32(src2)) (unsigned)

Xmax32S = 212

low32(dst) = max(low32(src1), low32(src2)) (signed)

Xmin64U = 213

dst = min(src1, src2) (unsigned)

Xmin64S = 214

dst = min(src1, src2) (signed)

Xmax64U = 215

dst = max(src1, src2) (unsigned)

Xmax64S = 216

dst = max(src1, src2) (signed)

XSelect32 = 217

low32(dst) = low32(cond) ? low32(if_nonzero) : low32(if_zero)

XSelect64 = 218

dst = low32(cond) ? if_nonzero : if_zero

ExtendedOp = 219

The extended-op opcode. An ExtendedOpcode follows this opcode.

Implementations

impl Opcode

pub const MAX: u8 = 219u8

The value of the maximum defined opcode.

impl Opcode

pub fn new(byte: u8) -> Option<Self>

Create a new Opcode from the given byte.

Returns None if byte is not a valid opcode.

pub unsafe fn unchecked_new(byte: u8) -> Self

Like new but does not check whether byte is a valid opcode.

Safety

It is unsafe to pass a byte that is not a valid opcode.

Trait Implementations

impl Clone for Opcode

fn clone(&self) -> Opcode

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Opcode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Decode for Opcode

Available on crate feature decode only.

fn decode<T>(bytecode: &mut T) -> Result<Self, T::Error>

where T: BytecodeStream,

Decode this type from the given bytecode stream.

impl Hash for Opcode

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for Opcode

fn cmp(&self, other: &Opcode) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

impl PartialEq for Opcode

fn eq(&self, other: &Opcode) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for Opcode

fn partial_cmp(&self, other: &Opcode) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for Opcode

impl Eq for Opcode

impl StructuralPartialEq for Opcode