cranelift_codegen/isa/riscv64/
lower.rs

1//! Lowering rules for Riscv64.
2use crate::ir::Inst as IRInst;
3use crate::isa::riscv64::inst::*;
4use crate::isa::riscv64::Riscv64Backend;
5use crate::machinst::lower::*;
6use crate::machinst::*;
7pub mod isle;
8
9//=============================================================================
10// Lowering-backend trait implementation.
11
12impl LowerBackend for Riscv64Backend {
13    type MInst = Inst;
14
15    fn lower(&self, ctx: &mut Lower<Inst>, ir_inst: IRInst) -> Option<InstOutput> {
16        isle::lower(ctx, self, ir_inst)
17    }
18
19    fn lower_branch(
20        &self,
21        ctx: &mut Lower<Inst>,
22        ir_inst: IRInst,
23        targets: &[MachLabel],
24    ) -> Option<()> {
25        isle::lower_branch(ctx, self, ir_inst, targets)
26    }
27
28    fn maybe_pinned_reg(&self) -> Option<Reg> {
29        // pinned register is a register that you want put anything in it.
30        // right now riscv64 not support this feature.
31        None
32    }
33
34    type FactFlowState = ();
35}