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cranelift_codegen/isa/riscv64/
lower.rs

1//! Lowering rules for Riscv64.
2use crate::ir::Inst as IRInst;
3use crate::isa::riscv64::Riscv64Backend;
4use crate::isa::riscv64::inst::*;
5use crate::machinst::*;
6pub mod isle;
7
8//=============================================================================
9// Lowering-backend trait implementation.
10
11impl LowerBackend for Riscv64Backend {
12    type MInst = Inst;
13
14    fn lower(&self, ctx: &mut Lower<Inst>, ir_inst: IRInst) -> Option<InstOutput> {
15        isle::lower(ctx, self, ir_inst)
16    }
17
18    fn lower_branch(
19        &self,
20        ctx: &mut Lower<Inst>,
21        ir_inst: IRInst,
22        targets: &[MachLabel],
23    ) -> Option<()> {
24        isle::lower_branch(ctx, self, ir_inst, targets)
25    }
26
27    fn maybe_pinned_reg(&self) -> Option<Reg> {
28        // pinned register is a register that you want put anything in it.
29        // right now riscv64 not support this feature.
30        None
31    }
32}