cranelift_codegen/isa/pulley_shared/inst/
regs.rs

1//! Pulley registers.
2
3use crate::machinst::{Reg, Writable};
4use regalloc2::{PReg, RegClass, VReg};
5
6#[inline]
7pub fn x_reg(enc: usize) -> Reg {
8    let p = PReg::new(enc, RegClass::Int);
9    let v = VReg::new(p.index(), p.class());
10    Reg::from(v)
11}
12
13#[inline]
14pub const fn px_reg(enc: usize) -> PReg {
15    PReg::new(enc, RegClass::Int)
16}
17
18#[inline]
19pub fn f_reg(enc: usize) -> Reg {
20    let p = PReg::new(enc, RegClass::Float);
21    let v = VReg::new(p.index(), p.class());
22    Reg::from(v)
23}
24
25#[inline]
26pub const fn pf_reg(enc: usize) -> PReg {
27    PReg::new(enc, RegClass::Float)
28}
29
30#[inline]
31pub fn v_reg(enc: usize) -> Reg {
32    let p = PReg::new(enc, RegClass::Vector);
33    let v = VReg::new(p.index(), p.class());
34    Reg::from(v)
35}
36
37#[inline]
38pub const fn pv_reg(enc: usize) -> PReg {
39    PReg::new(enc, RegClass::Vector)
40}
41
42macro_rules! define_registers {
43    (
44        $(
45            $reg:expr => $readable:ident, $writable:ident;
46        )*
47    ) => {
48        $(
49            #[inline]
50            #[allow(dead_code)]
51            pub fn $readable() -> Reg {
52                $reg
53            }
54
55            #[inline]
56            #[allow(dead_code)]
57            pub fn $writable() -> Writable<Reg> {
58                Writable::from_reg($readable())
59            }
60        )*
61    };
62}
63
64define_registers! {
65    x_reg(0) => x0, writable_x0;
66    x_reg(1) => x1, writable_x1;
67    x_reg(2) => x2, writable_x2;
68    x_reg(3) => x3, writable_x3;
69    x_reg(4) => x4, writable_x4;
70    x_reg(5) => x5, writable_x5;
71    x_reg(6) => x6, writable_x6;
72    x_reg(7) => x7, writable_x7;
73    x_reg(8) => x8, writable_x8;
74    x_reg(9) => x9, writable_x9;
75    x_reg(10) => x10, writable_x10;
76    x_reg(11) => x11, writable_x11;
77    x_reg(12) => x12, writable_x12;
78    x_reg(13) => x13, writable_x13;
79    x_reg(14) => x14, writable_x14;
80    x_reg(15) => x15, writable_x15;
81    x_reg(16) => x16, writable_x16;
82    x_reg(17) => x17, writable_x17;
83    x_reg(18) => x18, writable_x18;
84    x_reg(19) => x19, writable_x19;
85    x_reg(20) => x20, writable_x20;
86    x_reg(21) => x21, writable_x21;
87    x_reg(22) => x22, writable_x22;
88    x_reg(23) => x23, writable_x23;
89    x_reg(24) => x24, writable_x24;
90    x_reg(25) => x25, writable_x25;
91    x_reg(26) => x26, writable_x26;
92    x_reg(27) => x27, writable_x27;
93    x_reg(28) => x28, writable_x28;
94    x_reg(29) => x29, writable_x29;
95
96    x_reg(30) => stack_reg, writable_stack_reg;
97    x_reg(31) => spilltmp_reg, writable_spilltmp_reg;
98
99    f_reg(0) => f0, writable_f0;
100    f_reg(1) => f1, writable_f1;
101    f_reg(2) => f2, writable_f2;
102    f_reg(3) => f3, writable_f3;
103    f_reg(4) => f4, writable_f4;
104    f_reg(5) => f5, writable_f5;
105    f_reg(6) => f6, writable_f6;
106    f_reg(7) => f7, writable_f7;
107    f_reg(8) => f8, writable_f8;
108    f_reg(9) => f9, writable_f9;
109    f_reg(10) => f10, writable_f10;
110    f_reg(11) => f11, writable_f11;
111    f_reg(12) => f12, writable_f12;
112    f_reg(13) => f13, writable_f13;
113    f_reg(14) => f14, writable_f14;
114    f_reg(15) => f15, writable_f15;
115    f_reg(16) => f16, writable_f16;
116    f_reg(17) => f17, writable_f17;
117    f_reg(18) => f18, writable_f18;
118    f_reg(19) => f19, writable_f19;
119    f_reg(20) => f20, writable_f20;
120    f_reg(21) => f21, writable_f21;
121    f_reg(22) => f22, writable_f22;
122    f_reg(23) => f23, writable_f23;
123    f_reg(24) => f24, writable_f24;
124    f_reg(25) => f25, writable_f25;
125    f_reg(26) => f26, writable_f26;
126    f_reg(27) => f27, writable_f27;
127    f_reg(28) => f28, writable_f28;
128    f_reg(29) => f29, writable_f29;
129    f_reg(30) => f30, writable_f30;
130    f_reg(31) => f31, writable_f31;
131
132    v_reg(0) => v0, writable_v0;
133    v_reg(1) => v1, writable_v1;
134    v_reg(2) => v2, writable_v2;
135    v_reg(3) => v3, writable_v3;
136    v_reg(4) => v4, writable_v4;
137    v_reg(5) => v5, writable_v5;
138    v_reg(6) => v6, writable_v6;
139    v_reg(7) => v7, writable_v7;
140    v_reg(8) => v8, writable_v8;
141    v_reg(9) => v9, writable_v9;
142    v_reg(10) => v10, writable_v10;
143    v_reg(11) => v11, writable_v11;
144    v_reg(12) => v12, writable_v12;
145    v_reg(13) => v13, writable_v13;
146    v_reg(14) => v14, writable_v14;
147    v_reg(15) => v15, writable_v15;
148    v_reg(16) => v16, writable_v16;
149    v_reg(17) => v17, writable_v17;
150    v_reg(18) => v18, writable_v18;
151    v_reg(19) => v19, writable_v19;
152    v_reg(20) => v20, writable_v20;
153    v_reg(21) => v21, writable_v21;
154    v_reg(22) => v22, writable_v22;
155    v_reg(23) => v23, writable_v23;
156    v_reg(24) => v24, writable_v24;
157    v_reg(25) => v25, writable_v25;
158    v_reg(26) => v26, writable_v26;
159    v_reg(27) => v27, writable_v27;
160    v_reg(28) => v28, writable_v28;
161    v_reg(29) => v29, writable_v29;
162    v_reg(30) => v30, writable_v30;
163    v_reg(31) => v31, writable_v31;
164}
cranelift_codegen/isa/pulley_shared/inst/regs.rs

cranelift_codegen/isa/pulley_shared/inst/
regs.rs
