cranelift_codegen/isa/aarch64/
mod.rs

1//! ARM 64-bit Instruction Set Architecture.
2
3use crate::dominator_tree::DominatorTree;
4use crate::ir::{self, Function, Type};
5use crate::isa::aarch64::settings as aarch64_settings;
6#[cfg(feature = "unwind")]
7use crate::isa::unwind::systemv;
8use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey, TargetIsa};
9use crate::machinst::CompiledCode;
10use crate::machinst::{
11    CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode,
12    compile,
13};
14use crate::result::CodegenResult;
15use crate::settings as shared_settings;
16use alloc::string::String;
17use alloc::{boxed::Box, vec::Vec};
18use core::fmt;
19use cranelift_control::ControlPlane;
20use target_lexicon::{Aarch64Architecture, Architecture, Triple};
21
22// New backend:
23mod abi;
24pub mod inst;
25mod lower;
26pub mod settings;
27
28use self::inst::EmitInfo;
29
30/// An AArch64 backend.
31pub struct AArch64Backend {
32    triple: Triple,
33    flags: shared_settings::Flags,
34    isa_flags: aarch64_settings::Flags,
35}
36
37impl AArch64Backend {
38    /// Create a new AArch64 backend with the given (shared) flags.
39    pub fn new_with_flags(
40        triple: Triple,
41        flags: shared_settings::Flags,
42        isa_flags: aarch64_settings::Flags,
43    ) -> AArch64Backend {
44        AArch64Backend {
45            triple,
46            flags,
47            isa_flags,
48        }
49    }
50
51    /// This performs lowering to VCode, register-allocates the code, computes block layout and
52    /// finalizes branches. The result is ready for binary emission.
53    fn compile_vcode(
54        &self,
55        func: &Function,
56        domtree: &DominatorTree,
57        regalloc_ctx: &mut regalloc2::Ctx,
58        ctrl_plane: &mut ControlPlane,
59    ) -> CodegenResult<VCode<inst::Inst>> {
60        let emit_info = EmitInfo::new(self.flags.clone(), self.isa_flags.clone());
61        let sigs = SigSet::new::<abi::AArch64MachineDeps>(func, &self.flags)?;
62        let abi = abi::AArch64Callee::new(func, self, &self.isa_flags, &sigs)?;
63        compile::compile::<AArch64Backend>(
64            func,
65            domtree,
66            regalloc_ctx,
67            self,
68            abi,
69            emit_info,
70            sigs,
71            ctrl_plane,
72        )
73    }
74}
75
76impl TargetIsa for AArch64Backend {
77    fn compile_function(
78        &self,
79        func: &Function,
80        domtree: &DominatorTree,
81        regalloc_ctx: &mut regalloc2::Ctx,
82        want_disasm: bool,
83        ctrl_plane: &mut ControlPlane,
84    ) -> CodegenResult<CompiledCodeStencil> {
85        let vcode = self.compile_vcode(func, domtree, regalloc_ctx, ctrl_plane)?;
86
87        let emit_result = vcode.emit(&regalloc_ctx.output, want_disasm, &self.flags, ctrl_plane)?;
88        let value_labels_ranges = emit_result.value_labels_ranges;
89        let buffer = emit_result.buffer;
90
91        if let Some(disasm) = emit_result.disasm.as_ref() {
92            log::debug!("disassembly:\n{disasm}");
93        }
94
95        Ok(CompiledCodeStencil(CompiledCode {
96            buffer,
97            vcode: emit_result.disasm,
98            value_labels_ranges,
99            bb_starts: emit_result.bb_offsets,
100            bb_edges: emit_result.bb_edges,
101        }))
102    }
103
104    fn name(&self) -> &'static str {
105        "aarch64"
106    }
107
108    fn triple(&self) -> &Triple {
109        &self.triple
110    }
111
112    fn flags(&self) -> &shared_settings::Flags {
113        &self.flags
114    }
115
116    fn isa_flags(&self) -> Vec<shared_settings::Value> {
117        self.isa_flags.iter().collect()
118    }
119
120    fn isa_flags_hash_key(&self) -> IsaFlagsHashKey<'_> {
121        IsaFlagsHashKey(self.isa_flags.hash_key())
122    }
123
124    fn is_branch_protection_enabled(&self) -> bool {
125        self.isa_flags.use_bti()
126    }
127
128    fn dynamic_vector_bytes(&self, _dyn_ty: Type) -> u32 {
129        16
130    }
131
132    #[cfg(feature = "unwind")]
133    fn emit_unwind_info(
134        &self,
135        result: &CompiledCode,
136        kind: crate::isa::unwind::UnwindInfoKind,
137    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
138        use crate::isa::unwind::UnwindInfo;
139        use crate::isa::unwind::UnwindInfoKind;
140        Ok(match kind {
141            UnwindInfoKind::SystemV => {
142                let mapper = self::inst::unwind::systemv::RegisterMapper;
143                Some(UnwindInfo::SystemV(
144                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
145                        &result.buffer.unwind_info[..],
146                        result.buffer.data().len(),
147                        &mapper,
148                    )?,
149                ))
150            }
151            UnwindInfoKind::Windows => Some(UnwindInfo::WindowsArm64(
152                crate::isa::unwind::winarm64::create_unwind_info_from_insts(
153                    &result.buffer.unwind_info[..],
154                )?,
155            )),
156            _ => None,
157        })
158    }
159
160    #[cfg(feature = "unwind")]
161    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
162        if self.isa_flags.sign_return_address()
163            && self.isa_flags.sign_return_address_with_bkey()
164            && !self.triple.operating_system.is_like_darwin()
165        {
166            unimplemented!(
167                "Specifying that the B key is used with pointer authentication instructions in the CIE is not implemented."
168            );
169        }
170
171        Some(inst::unwind::systemv::create_cie())
172    }
173
174    fn text_section_builder(&self, num_funcs: usize) -> Box<dyn TextSectionBuilder> {
175        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
176    }
177
178    #[cfg(feature = "unwind")]
179    fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
180        inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
181    }
182
183    fn function_alignment(&self) -> FunctionAlignment {
184        inst::Inst::function_alignment()
185    }
186
187    fn page_size_align_log2(&self) -> u8 {
188        if self.triple().operating_system.is_like_darwin() {
189            debug_assert_eq!(1 << 14, 0x4000);
190            14
191        } else {
192            debug_assert_eq!(1 << 16, 0x10000);
193            16
194        }
195    }
196
197    #[cfg(feature = "disas")]
198    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
199        use capstone::prelude::*;
200        let mut cs = Capstone::new()
201            .arm64()
202            .mode(arch::arm64::ArchMode::Arm)
203            .detail(true)
204            .build()?;
205        // AArch64 uses inline constants rather than a separate constant pool right now.
206        // Without this option, Capstone will stop disassembling as soon as it sees
207        // an inline constant that is not also a valid instruction. With this option,
208        // Capstone will print a `.byte` directive with the bytes of the inline constant
209        // and continue to the next instruction.
210        cs.set_skipdata(true)?;
211        Ok(cs)
212    }
213
214    fn pretty_print_reg(&self, reg: Reg, _size: u8) -> String {
215        inst::regs::pretty_print_reg(reg)
216    }
217
218    fn has_native_fma(&self) -> bool {
219        true
220    }
221
222    fn has_round(&self) -> bool {
223        true
224    }
225
226    fn has_blendv_lowering(&self, _: Type) -> bool {
227        false
228    }
229
230    fn has_x86_pshufb_lowering(&self) -> bool {
231        false
232    }
233
234    fn has_x86_pmulhrsw_lowering(&self) -> bool {
235        false
236    }
237
238    fn has_x86_pmaddubsw_lowering(&self) -> bool {
239        false
240    }
241
242    fn default_argument_extension(&self) -> ir::ArgumentExtension {
243        // This is copied/carried over from a historical piece of code in
244        // Wasmtime:
245        //
246        // https://github.com/bytecodealliance/wasmtime/blob/a018a5a9addb77d5998021a0150192aa955c71bf/crates/cranelift/src/lib.rs#L366-L374
247        //
248        // Whether or not it is still applicable here is unsure, but it's left
249        // the same as-is for now to reduce the likelihood of problems arising.
250        ir::ArgumentExtension::Uext
251    }
252}
253
254impl fmt::Display for AArch64Backend {
255    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
256        f.debug_struct("MachBackend")
257            .field("name", &self.name())
258            .field("triple", &self.triple())
259            .field("flags", &format!("{}", self.flags()))
260            .finish()
261    }
262}
263
264/// Create a new `isa::Builder`.
265pub fn isa_builder(triple: Triple) -> IsaBuilder {
266    assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64));
267    IsaBuilder {
268        triple,
269        setup: aarch64_settings::builder(),
270        constructor: |triple, shared_flags, builder| {
271            let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder);
272            let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags);
273            Ok(backend.wrapped())
274        },
275    }
276}
cranelift_codegen/isa/aarch64/mod.rs

cranelift_codegen/isa/aarch64/
mod.rs
