cranelift_codegen/isa/aarch64/
mod.rs

1//! ARM 64-bit Instruction Set Architecture.
2
3use crate::dominator_tree::DominatorTree;
4use crate::ir::{self, Function, Type};
5use crate::isa::aarch64::settings as aarch64_settings;
6#[cfg(feature = "unwind")]
7use crate::isa::unwind::systemv;
8use crate::isa::{Builder as IsaBuilder, FunctionAlignment, IsaFlagsHashKey, TargetIsa};
9#[cfg(feature = "unwind")]
10use crate::machinst::CompiledCode;
11use crate::machinst::{
12    CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet, TextSectionBuilder, VCode,
13    compile,
14};
15use crate::result::CodegenResult;
16use crate::settings as shared_settings;
17use alloc::string::String;
18use alloc::{boxed::Box, vec::Vec};
19use core::fmt;
20use cranelift_control::ControlPlane;
21use target_lexicon::{Aarch64Architecture, Architecture, Triple};
22
23// New backend:
24mod abi;
25pub mod inst;
26mod lower;
27pub mod settings;
28
29use self::inst::EmitInfo;
30
31/// An AArch64 backend.
32pub struct AArch64Backend {
33    triple: Triple,
34    flags: shared_settings::Flags,
35    isa_flags: aarch64_settings::Flags,
36}
37
38impl AArch64Backend {
39    /// Create a new AArch64 backend with the given (shared) flags.
40    pub fn new_with_flags(
41        triple: Triple,
42        flags: shared_settings::Flags,
43        isa_flags: aarch64_settings::Flags,
44    ) -> AArch64Backend {
45        AArch64Backend {
46            triple,
47            flags,
48            isa_flags,
49        }
50    }
51
52    /// This performs lowering to VCode, register-allocates the code, computes block layout and
53    /// finalizes branches. The result is ready for binary emission.
54    fn compile_vcode(
55        &self,
56        func: &Function,
57        domtree: &DominatorTree,
58        regalloc_ctx: &mut regalloc2::Ctx,
59        ctrl_plane: &mut ControlPlane,
60    ) -> CodegenResult<VCode<inst::Inst>> {
61        let emit_info = EmitInfo::new(self.flags.clone(), self.isa_flags.clone());
62        let sigs = SigSet::new::<abi::AArch64MachineDeps>(func, &self.flags)?;
63        let abi = abi::AArch64Callee::new(func, self, &self.isa_flags, &sigs)?;
64        compile::compile::<AArch64Backend>(
65            func,
66            domtree,
67            regalloc_ctx,
68            self,
69            abi,
70            emit_info,
71            sigs,
72            ctrl_plane,
73        )
74    }
75}
76
77impl TargetIsa for AArch64Backend {
78    fn compile_function(
79        &self,
80        func: &Function,
81        domtree: &DominatorTree,
82        regalloc_ctx: &mut regalloc2::Ctx,
83        want_disasm: bool,
84        ctrl_plane: &mut ControlPlane,
85    ) -> CodegenResult<CompiledCodeStencil> {
86        let vcode = self.compile_vcode(func, domtree, regalloc_ctx, ctrl_plane)?;
87
88        let emit_result = vcode.emit(&regalloc_ctx.output, want_disasm, &self.flags, ctrl_plane)?;
89        let value_labels_ranges = emit_result.value_labels_ranges;
90        let buffer = emit_result.buffer;
91
92        if let Some(disasm) = emit_result.disasm.as_ref() {
93            log::debug!("disassembly:\n{disasm}");
94        }
95
96        Ok(CompiledCodeStencil {
97            buffer,
98            vcode: emit_result.disasm,
99            value_labels_ranges,
100            bb_starts: emit_result.bb_offsets,
101            bb_edges: emit_result.bb_edges,
102        })
103    }
104
105    fn name(&self) -> &'static str {
106        "aarch64"
107    }
108
109    fn triple(&self) -> &Triple {
110        &self.triple
111    }
112
113    fn flags(&self) -> &shared_settings::Flags {
114        &self.flags
115    }
116
117    fn isa_flags(&self) -> Vec<shared_settings::Value> {
118        self.isa_flags.iter().collect()
119    }
120
121    fn isa_flags_hash_key(&self) -> IsaFlagsHashKey<'_> {
122        IsaFlagsHashKey(self.isa_flags.hash_key())
123    }
124
125    fn is_branch_protection_enabled(&self) -> bool {
126        self.isa_flags.use_bti()
127    }
128
129    fn dynamic_vector_bytes(&self, _dyn_ty: Type) -> u32 {
130        16
131    }
132
133    #[cfg(feature = "unwind")]
134    fn emit_unwind_info(
135        &self,
136        result: &CompiledCode,
137        kind: crate::isa::unwind::UnwindInfoKind,
138    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
139        use crate::isa::unwind::UnwindInfo;
140        use crate::isa::unwind::UnwindInfoKind;
141        Ok(match kind {
142            UnwindInfoKind::SystemV => {
143                let mapper = self::inst::unwind::systemv::RegisterMapper;
144                Some(UnwindInfo::SystemV(
145                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
146                        &result.buffer.unwind_info[..],
147                        result.buffer.data().len(),
148                        &mapper,
149                    )?,
150                ))
151            }
152            UnwindInfoKind::Windows => Some(UnwindInfo::WindowsArm64(
153                crate::isa::unwind::winarm64::create_unwind_info_from_insts(
154                    &result.buffer.unwind_info[..],
155                )?,
156            )),
157            _ => None,
158        })
159    }
160
161    #[cfg(feature = "unwind")]
162    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
163        if self.isa_flags.sign_return_address()
164            && self.isa_flags.sign_return_address_with_bkey()
165            && !self.triple.operating_system.is_like_darwin()
166        {
167            unimplemented!(
168                "Specifying that the B key is used with pointer authentication instructions in the CIE is not implemented."
169            );
170        }
171
172        Some(inst::unwind::systemv::create_cie())
173    }
174
175    fn text_section_builder(&self, num_funcs: usize) -> Box<dyn TextSectionBuilder> {
176        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
177    }
178
179    #[cfg(feature = "unwind")]
180    fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
181        inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
182    }
183
184    fn function_alignment(&self) -> FunctionAlignment {
185        inst::Inst::function_alignment()
186    }
187
188    fn page_size_align_log2(&self) -> u8 {
189        if self.triple().operating_system.is_like_darwin() {
190            debug_assert_eq!(1 << 14, 0x4000);
191            14
192        } else {
193            debug_assert_eq!(1 << 16, 0x10000);
194            16
195        }
196    }
197
198    #[cfg(feature = "disas")]
199    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
200        use capstone::prelude::*;
201        let mut cs = Capstone::new()
202            .arm64()
203            .mode(arch::arm64::ArchMode::Arm)
204            .detail(true)
205            .build()?;
206        // AArch64 uses inline constants rather than a separate constant pool right now.
207        // Without this option, Capstone will stop disassembling as soon as it sees
208        // an inline constant that is not also a valid instruction. With this option,
209        // Capstone will print a `.byte` directive with the bytes of the inline constant
210        // and continue to the next instruction.
211        cs.set_skipdata(true)?;
212        Ok(cs)
213    }
214
215    fn pretty_print_reg(&self, reg: Reg, _size: u8) -> String {
216        inst::regs::pretty_print_reg(reg)
217    }
218
219    fn has_native_fma(&self) -> bool {
220        true
221    }
222
223    fn has_round(&self) -> bool {
224        true
225    }
226
227    fn has_blendv_lowering(&self, _: Type) -> bool {
228        false
229    }
230
231    fn has_x86_pshufb_lowering(&self) -> bool {
232        false
233    }
234
235    fn has_x86_pmulhrsw_lowering(&self) -> bool {
236        false
237    }
238
239    fn has_x86_pmaddubsw_lowering(&self) -> bool {
240        false
241    }
242
243    fn default_argument_extension(&self) -> ir::ArgumentExtension {
244        // This is copied/carried over from a historical piece of code in
245        // Wasmtime:
246        //
247        // https://github.com/bytecodealliance/wasmtime/blob/a018a5a9addb77d5998021a0150192aa955c71bf/crates/cranelift/src/lib.rs#L366-L374
248        //
249        // Whether or not it is still applicable here is unsure, but it's left
250        // the same as-is for now to reduce the likelihood of problems arising.
251        ir::ArgumentExtension::Uext
252    }
253}
254
255impl fmt::Display for AArch64Backend {
256    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
257        f.debug_struct("MachBackend")
258            .field("name", &self.name())
259            .field("triple", &self.triple())
260            .field("flags", &format!("{}", self.flags()))
261            .finish()
262    }
263}
264
265/// Create a new `isa::Builder`.
266pub fn isa_builder(triple: Triple) -> IsaBuilder {
267    assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64));
268    IsaBuilder {
269        triple,
270        setup: aarch64_settings::builder(),
271        constructor: |triple, shared_flags, builder| {
272            let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder);
273            let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags);
274            Ok(backend.wrapped())
275        },
276    }
277}
cranelift_codegen/isa/aarch64/mod.rs

cranelift_codegen/isa/aarch64/
mod.rs
