1use crate::binemit::{Addend, CodeOffset, Reloc};
4use crate::ir::types::{F16, F32, F64, F128, I8, I8X16, I16, I32, I64, I128};
5use crate::ir::{MemFlags, Type, types};
6use crate::isa::{CallConv, FunctionAlignment};
7use crate::machinst::*;
8use crate::{CodegenError, CodegenResult, settings};
9
10use crate::machinst::{PrettyPrint, Reg, RegClass, Writable};
11
12use alloc::vec::Vec;
13use core::slice;
14use smallvec::{SmallVec, smallvec};
15use std::fmt::Write;
16use std::string::{String, ToString};
17
18pub(crate) mod regs;
19pub(crate) use self::regs::*;
20pub mod imms;
21pub use self::imms::*;
22pub mod args;
23pub use self::args::*;
24pub mod emit;
25pub(crate) use self::emit::*;
26use crate::isa::aarch64::abi::AArch64MachineDeps;
27
28pub(crate) mod unwind;
29
30#[cfg(test)]
31mod emit_tests;
32
33pub use crate::isa::aarch64::lower::isle::generated_code::{
37 ALUOp, ALUOp3, AMode, APIKey, AtomicRMWLoopOp, AtomicRMWOp, BitOp, BranchTargetType, FPUOp1,
38 FPUOp2, FPUOp3, FpuRoundMode, FpuToIntOp, IntToFpuOp, MInst as Inst, MoveWideOp, VecALUModOp,
39 VecALUOp, VecExtendOp, VecLanesOp, VecMisc2, VecPairOp, VecRRLongOp, VecRRNarrowOp,
40 VecRRPairLongOp, VecRRRLongModOp, VecRRRLongOp, VecShiftImmModOp, VecShiftImmOp,
41};
42
43#[derive(Copy, Clone, Debug)]
45pub enum FPUOpRI {
46 UShr32(FPURightShiftImm),
48 UShr64(FPURightShiftImm),
50}
51
52#[derive(Copy, Clone, Debug)]
56pub enum FPUOpRIMod {
57 Sli32(FPULeftShiftImm),
59 Sli64(FPULeftShiftImm),
61}
62
63impl BitOp {
64 pub fn op_str(&self) -> &'static str {
66 match self {
67 BitOp::RBit => "rbit",
68 BitOp::Clz => "clz",
69 BitOp::Cls => "cls",
70 BitOp::Rev16 => "rev16",
71 BitOp::Rev32 => "rev32",
72 BitOp::Rev64 => "rev64",
73 }
74 }
75}
76
77#[derive(Clone, Debug)]
80pub struct ReturnCallInfo<T> {
81 pub dest: T,
83 pub uses: CallArgList,
85 pub new_stack_arg_size: u32,
89 pub key: Option<APIKey>,
91}
92
93fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
94 let mut count = 0;
95 for _ in 0..num_half_words {
96 if value & 0xffff == 0 {
97 count += 1;
98 }
99 value >>= 16;
100 }
101
102 count
103}
104
105impl Inst {
106 pub fn load_constant(rd: Writable<Reg>, value: u64) -> SmallVec<[Inst; 4]> {
109 if let Some(imm) = MoveWideConst::maybe_from_u64(value) {
114 smallvec![Inst::MovWide {
116 op: MoveWideOp::MovZ,
117 rd,
118 imm,
119 size: OperandSize::Size64
120 }]
121 } else if let Some(imm) = MoveWideConst::maybe_from_u64(!value) {
122 smallvec![Inst::MovWide {
124 op: MoveWideOp::MovN,
125 rd,
126 imm,
127 size: OperandSize::Size64
128 }]
129 } else if let Some(imml) = ImmLogic::maybe_from_u64(value, I64) {
130 smallvec![Inst::AluRRImmLogic {
132 alu_op: ALUOp::Orr,
133 size: OperandSize::Size64,
134 rd,
135 rn: zero_reg(),
136 imml,
137 }]
138 } else {
139 let mut insts = smallvec![];
140
141 let (num_half_words, size, negated) = if value >> 32 == 0 {
143 (2, OperandSize::Size32, (!value << 32) >> 32)
144 } else {
145 (4, OperandSize::Size64, !value)
146 };
147
148 let first_is_inverted = count_zero_half_words(negated, num_half_words)
151 > count_zero_half_words(value, num_half_words);
152
153 let ignored_halfword = if first_is_inverted { 0xffff } else { 0 };
156
157 let halfwords: SmallVec<[_; 4]> = (0..num_half_words)
158 .filter_map(|i| {
159 let imm16 = (value >> (16 * i)) & 0xffff;
160 if imm16 == ignored_halfword {
161 None
162 } else {
163 Some((i, imm16))
164 }
165 })
166 .collect();
167
168 let mut prev_result = None;
169 for (i, imm16) in halfwords {
170 let shift = i * 16;
171
172 if let Some(rn) = prev_result {
173 let imm = MoveWideConst::maybe_with_shift(imm16 as u16, shift).unwrap();
174 insts.push(Inst::MovK { rd, rn, imm, size });
175 } else {
176 if first_is_inverted {
177 let imm =
178 MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, shift)
179 .unwrap();
180 insts.push(Inst::MovWide {
181 op: MoveWideOp::MovN,
182 rd,
183 imm,
184 size,
185 });
186 } else {
187 let imm = MoveWideConst::maybe_with_shift(imm16 as u16, shift).unwrap();
188 insts.push(Inst::MovWide {
189 op: MoveWideOp::MovZ,
190 rd,
191 imm,
192 size,
193 });
194 }
195 }
196
197 prev_result = Some(rd.to_reg());
198 }
199
200 assert!(prev_result.is_some());
201
202 insts
203 }
204 }
205
206 pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
208 match ty {
209 I8 => Inst::ULoad8 {
210 rd: into_reg,
211 mem,
212 flags,
213 },
214 I16 => Inst::ULoad16 {
215 rd: into_reg,
216 mem,
217 flags,
218 },
219 I32 => Inst::ULoad32 {
220 rd: into_reg,
221 mem,
222 flags,
223 },
224 I64 => Inst::ULoad64 {
225 rd: into_reg,
226 mem,
227 flags,
228 },
229 _ => {
230 if ty.is_vector() || ty.is_float() {
231 let bits = ty_bits(ty);
232 let rd = into_reg;
233
234 match bits {
235 128 => Inst::FpuLoad128 { rd, mem, flags },
236 64 => Inst::FpuLoad64 { rd, mem, flags },
237 32 => Inst::FpuLoad32 { rd, mem, flags },
238 16 => Inst::FpuLoad16 { rd, mem, flags },
239 _ => unimplemented!("gen_load({})", ty),
240 }
241 } else {
242 unimplemented!("gen_load({})", ty);
243 }
244 }
245 }
246 }
247
248 pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
250 match ty {
251 I8 => Inst::Store8 {
252 rd: from_reg,
253 mem,
254 flags,
255 },
256 I16 => Inst::Store16 {
257 rd: from_reg,
258 mem,
259 flags,
260 },
261 I32 => Inst::Store32 {
262 rd: from_reg,
263 mem,
264 flags,
265 },
266 I64 => Inst::Store64 {
267 rd: from_reg,
268 mem,
269 flags,
270 },
271 _ => {
272 if ty.is_vector() || ty.is_float() {
273 let bits = ty_bits(ty);
274 let rd = from_reg;
275
276 match bits {
277 128 => Inst::FpuStore128 { rd, mem, flags },
278 64 => Inst::FpuStore64 { rd, mem, flags },
279 32 => Inst::FpuStore32 { rd, mem, flags },
280 16 => Inst::FpuStore16 { rd, mem, flags },
281 _ => unimplemented!("gen_store({})", ty),
282 }
283 } else {
284 unimplemented!("gen_store({})", ty);
285 }
286 }
287 }
288 }
289
290 pub fn mem_type(&self) -> Option<Type> {
294 match self {
295 Inst::ULoad8 { .. } => Some(I8),
296 Inst::SLoad8 { .. } => Some(I8),
297 Inst::ULoad16 { .. } => Some(I16),
298 Inst::SLoad16 { .. } => Some(I16),
299 Inst::ULoad32 { .. } => Some(I32),
300 Inst::SLoad32 { .. } => Some(I32),
301 Inst::ULoad64 { .. } => Some(I64),
302 Inst::FpuLoad16 { .. } => Some(F16),
303 Inst::FpuLoad32 { .. } => Some(F32),
304 Inst::FpuLoad64 { .. } => Some(F64),
305 Inst::FpuLoad128 { .. } => Some(I8X16),
306 Inst::Store8 { .. } => Some(I8),
307 Inst::Store16 { .. } => Some(I16),
308 Inst::Store32 { .. } => Some(I32),
309 Inst::Store64 { .. } => Some(I64),
310 Inst::FpuStore16 { .. } => Some(F16),
311 Inst::FpuStore32 { .. } => Some(F32),
312 Inst::FpuStore64 { .. } => Some(F64),
313 Inst::FpuStore128 { .. } => Some(I8X16),
314 _ => None,
315 }
316 }
317}
318
319fn memarg_operands(memarg: &mut AMode, collector: &mut impl OperandVisitor) {
323 match memarg {
324 AMode::Unscaled { rn, .. } | AMode::UnsignedOffset { rn, .. } => {
325 collector.reg_use(rn);
326 }
327 AMode::RegReg { rn, rm, .. }
328 | AMode::RegScaled { rn, rm, .. }
329 | AMode::RegScaledExtended { rn, rm, .. }
330 | AMode::RegExtended { rn, rm, .. } => {
331 collector.reg_use(rn);
332 collector.reg_use(rm);
333 }
334 AMode::Label { .. } => {}
335 AMode::SPPreIndexed { .. } | AMode::SPPostIndexed { .. } => {}
336 AMode::FPOffset { .. } | AMode::IncomingArg { .. } => {}
337 AMode::SPOffset { .. } | AMode::SlotOffset { .. } => {}
338 AMode::RegOffset { rn, .. } => {
339 collector.reg_use(rn);
340 }
341 AMode::Const { .. } => {}
342 }
343}
344
345fn pairmemarg_operands(pairmemarg: &mut PairAMode, collector: &mut impl OperandVisitor) {
346 match pairmemarg {
347 PairAMode::SignedOffset { reg, .. } => {
348 collector.reg_use(reg);
349 }
350 PairAMode::SPPreIndexed { .. } | PairAMode::SPPostIndexed { .. } => {}
351 }
352}
353
354fn aarch64_get_operands(inst: &mut Inst, collector: &mut impl OperandVisitor) {
355 match inst {
356 Inst::AluRRR { rd, rn, rm, .. } => {
357 collector.reg_def(rd);
358 collector.reg_use(rn);
359 collector.reg_use(rm);
360 }
361 Inst::AluRRRR { rd, rn, rm, ra, .. } => {
362 collector.reg_def(rd);
363 collector.reg_use(rn);
364 collector.reg_use(rm);
365 collector.reg_use(ra);
366 }
367 Inst::AluRRImm12 { rd, rn, .. } => {
368 collector.reg_def(rd);
369 collector.reg_use(rn);
370 }
371 Inst::AluRRImmLogic { rd, rn, .. } => {
372 collector.reg_def(rd);
373 collector.reg_use(rn);
374 }
375 Inst::AluRRImmShift { rd, rn, .. } => {
376 collector.reg_def(rd);
377 collector.reg_use(rn);
378 }
379 Inst::AluRRRShift { rd, rn, rm, .. } => {
380 collector.reg_def(rd);
381 collector.reg_use(rn);
382 collector.reg_use(rm);
383 }
384 Inst::AluRRRExtend { rd, rn, rm, .. } => {
385 collector.reg_def(rd);
386 collector.reg_use(rn);
387 collector.reg_use(rm);
388 }
389 Inst::BitRR { rd, rn, .. } => {
390 collector.reg_def(rd);
391 collector.reg_use(rn);
392 }
393 Inst::ULoad8 { rd, mem, .. }
394 | Inst::SLoad8 { rd, mem, .. }
395 | Inst::ULoad16 { rd, mem, .. }
396 | Inst::SLoad16 { rd, mem, .. }
397 | Inst::ULoad32 { rd, mem, .. }
398 | Inst::SLoad32 { rd, mem, .. }
399 | Inst::ULoad64 { rd, mem, .. } => {
400 collector.reg_def(rd);
401 memarg_operands(mem, collector);
402 }
403 Inst::Store8 { rd, mem, .. }
404 | Inst::Store16 { rd, mem, .. }
405 | Inst::Store32 { rd, mem, .. }
406 | Inst::Store64 { rd, mem, .. } => {
407 collector.reg_use(rd);
408 memarg_operands(mem, collector);
409 }
410 Inst::StoreP64 { rt, rt2, mem, .. } => {
411 collector.reg_use(rt);
412 collector.reg_use(rt2);
413 pairmemarg_operands(mem, collector);
414 }
415 Inst::LoadP64 { rt, rt2, mem, .. } => {
416 collector.reg_def(rt);
417 collector.reg_def(rt2);
418 pairmemarg_operands(mem, collector);
419 }
420 Inst::Mov { rd, rm, .. } => {
421 collector.reg_def(rd);
422 collector.reg_use(rm);
423 }
424 Inst::MovFromPReg { rd, rm } => {
425 debug_assert!(rd.to_reg().is_virtual());
426 collector.reg_def(rd);
427 collector.reg_fixed_nonallocatable(*rm);
428 }
429 Inst::MovToPReg { rd, rm } => {
430 debug_assert!(rm.is_virtual());
431 collector.reg_fixed_nonallocatable(*rd);
432 collector.reg_use(rm);
433 }
434 Inst::MovK { rd, rn, .. } => {
435 collector.reg_use(rn);
436 collector.reg_reuse_def(rd, 0); }
438 Inst::MovWide { rd, .. } => {
439 collector.reg_def(rd);
440 }
441 Inst::CSel { rd, rn, rm, .. } => {
442 collector.reg_def(rd);
443 collector.reg_use(rn);
444 collector.reg_use(rm);
445 }
446 Inst::CSNeg { rd, rn, rm, .. } => {
447 collector.reg_def(rd);
448 collector.reg_use(rn);
449 collector.reg_use(rm);
450 }
451 Inst::CSet { rd, .. } | Inst::CSetm { rd, .. } => {
452 collector.reg_def(rd);
453 }
454 Inst::CCmp { rn, rm, .. } => {
455 collector.reg_use(rn);
456 collector.reg_use(rm);
457 }
458 Inst::CCmpImm { rn, .. } => {
459 collector.reg_use(rn);
460 }
461 Inst::AtomicRMWLoop {
462 op,
463 addr,
464 operand,
465 oldval,
466 scratch1,
467 scratch2,
468 ..
469 } => {
470 collector.reg_fixed_use(addr, xreg(25));
471 collector.reg_fixed_use(operand, xreg(26));
472 collector.reg_fixed_def(oldval, xreg(27));
473 collector.reg_fixed_def(scratch1, xreg(24));
474 if *op != AtomicRMWLoopOp::Xchg {
475 collector.reg_fixed_def(scratch2, xreg(28));
476 }
477 }
478 Inst::AtomicRMW { rs, rt, rn, .. } => {
479 collector.reg_use(rs);
480 collector.reg_def(rt);
481 collector.reg_use(rn);
482 }
483 Inst::AtomicCAS { rd, rs, rt, rn, .. } => {
484 collector.reg_reuse_def(rd, 1); collector.reg_use(rs);
486 collector.reg_use(rt);
487 collector.reg_use(rn);
488 }
489 Inst::AtomicCASLoop {
490 addr,
491 expected,
492 replacement,
493 oldval,
494 scratch,
495 ..
496 } => {
497 collector.reg_fixed_use(addr, xreg(25));
498 collector.reg_fixed_use(expected, xreg(26));
499 collector.reg_fixed_use(replacement, xreg(28));
500 collector.reg_fixed_def(oldval, xreg(27));
501 collector.reg_fixed_def(scratch, xreg(24));
502 }
503 Inst::LoadAcquire { rt, rn, .. } => {
504 collector.reg_use(rn);
505 collector.reg_def(rt);
506 }
507 Inst::StoreRelease { rt, rn, .. } => {
508 collector.reg_use(rn);
509 collector.reg_use(rt);
510 }
511 Inst::Fence {} | Inst::Csdb {} => {}
512 Inst::FpuMove32 { rd, rn } => {
513 collector.reg_def(rd);
514 collector.reg_use(rn);
515 }
516 Inst::FpuMove64 { rd, rn } => {
517 collector.reg_def(rd);
518 collector.reg_use(rn);
519 }
520 Inst::FpuMove128 { rd, rn } => {
521 collector.reg_def(rd);
522 collector.reg_use(rn);
523 }
524 Inst::FpuMoveFromVec { rd, rn, .. } => {
525 collector.reg_def(rd);
526 collector.reg_use(rn);
527 }
528 Inst::FpuExtend { rd, rn, .. } => {
529 collector.reg_def(rd);
530 collector.reg_use(rn);
531 }
532 Inst::FpuRR { rd, rn, .. } => {
533 collector.reg_def(rd);
534 collector.reg_use(rn);
535 }
536 Inst::FpuRRR { rd, rn, rm, .. } => {
537 collector.reg_def(rd);
538 collector.reg_use(rn);
539 collector.reg_use(rm);
540 }
541 Inst::FpuRRI { rd, rn, .. } => {
542 collector.reg_def(rd);
543 collector.reg_use(rn);
544 }
545 Inst::FpuRRIMod { rd, ri, rn, .. } => {
546 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
548 collector.reg_use(rn);
549 }
550 Inst::FpuRRRR { rd, rn, rm, ra, .. } => {
551 collector.reg_def(rd);
552 collector.reg_use(rn);
553 collector.reg_use(rm);
554 collector.reg_use(ra);
555 }
556 Inst::VecMisc { rd, rn, .. } => {
557 collector.reg_def(rd);
558 collector.reg_use(rn);
559 }
560
561 Inst::VecLanes { rd, rn, .. } => {
562 collector.reg_def(rd);
563 collector.reg_use(rn);
564 }
565 Inst::VecShiftImm { rd, rn, .. } => {
566 collector.reg_def(rd);
567 collector.reg_use(rn);
568 }
569 Inst::VecShiftImmMod { rd, ri, rn, .. } => {
570 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
572 collector.reg_use(rn);
573 }
574 Inst::VecExtract { rd, rn, rm, .. } => {
575 collector.reg_def(rd);
576 collector.reg_use(rn);
577 collector.reg_use(rm);
578 }
579 Inst::VecTbl { rd, rn, rm } => {
580 collector.reg_use(rn);
581 collector.reg_use(rm);
582 collector.reg_def(rd);
583 }
584 Inst::VecTblExt { rd, ri, rn, rm } => {
585 collector.reg_use(rn);
586 collector.reg_use(rm);
587 collector.reg_reuse_def(rd, 3); collector.reg_use(ri);
589 }
590
591 Inst::VecTbl2 { rd, rn, rn2, rm } => {
592 collector.reg_fixed_use(rn, vreg(30));
596 collector.reg_fixed_use(rn2, vreg(31));
597 collector.reg_use(rm);
598 collector.reg_def(rd);
599 }
600 Inst::VecTbl2Ext {
601 rd,
602 ri,
603 rn,
604 rn2,
605 rm,
606 } => {
607 collector.reg_fixed_use(rn, vreg(30));
611 collector.reg_fixed_use(rn2, vreg(31));
612 collector.reg_use(rm);
613 collector.reg_reuse_def(rd, 4); collector.reg_use(ri);
615 }
616 Inst::VecLoadReplicate { rd, rn, .. } => {
617 collector.reg_def(rd);
618 collector.reg_use(rn);
619 }
620 Inst::VecCSel { rd, rn, rm, .. } => {
621 collector.reg_def(rd);
622 collector.reg_use(rn);
623 collector.reg_use(rm);
624 }
625 Inst::FpuCmp { rn, rm, .. } => {
626 collector.reg_use(rn);
627 collector.reg_use(rm);
628 }
629 Inst::FpuLoad16 { rd, mem, .. } => {
630 collector.reg_def(rd);
631 memarg_operands(mem, collector);
632 }
633 Inst::FpuLoad32 { rd, mem, .. } => {
634 collector.reg_def(rd);
635 memarg_operands(mem, collector);
636 }
637 Inst::FpuLoad64 { rd, mem, .. } => {
638 collector.reg_def(rd);
639 memarg_operands(mem, collector);
640 }
641 Inst::FpuLoad128 { rd, mem, .. } => {
642 collector.reg_def(rd);
643 memarg_operands(mem, collector);
644 }
645 Inst::FpuStore16 { rd, mem, .. } => {
646 collector.reg_use(rd);
647 memarg_operands(mem, collector);
648 }
649 Inst::FpuStore32 { rd, mem, .. } => {
650 collector.reg_use(rd);
651 memarg_operands(mem, collector);
652 }
653 Inst::FpuStore64 { rd, mem, .. } => {
654 collector.reg_use(rd);
655 memarg_operands(mem, collector);
656 }
657 Inst::FpuStore128 { rd, mem, .. } => {
658 collector.reg_use(rd);
659 memarg_operands(mem, collector);
660 }
661 Inst::FpuLoadP64 { rt, rt2, mem, .. } => {
662 collector.reg_def(rt);
663 collector.reg_def(rt2);
664 pairmemarg_operands(mem, collector);
665 }
666 Inst::FpuStoreP64 { rt, rt2, mem, .. } => {
667 collector.reg_use(rt);
668 collector.reg_use(rt2);
669 pairmemarg_operands(mem, collector);
670 }
671 Inst::FpuLoadP128 { rt, rt2, mem, .. } => {
672 collector.reg_def(rt);
673 collector.reg_def(rt2);
674 pairmemarg_operands(mem, collector);
675 }
676 Inst::FpuStoreP128 { rt, rt2, mem, .. } => {
677 collector.reg_use(rt);
678 collector.reg_use(rt2);
679 pairmemarg_operands(mem, collector);
680 }
681 Inst::FpuToInt { rd, rn, .. } => {
682 collector.reg_def(rd);
683 collector.reg_use(rn);
684 }
685 Inst::IntToFpu { rd, rn, .. } => {
686 collector.reg_def(rd);
687 collector.reg_use(rn);
688 }
689 Inst::FpuCSel16 { rd, rn, rm, .. }
690 | Inst::FpuCSel32 { rd, rn, rm, .. }
691 | Inst::FpuCSel64 { rd, rn, rm, .. } => {
692 collector.reg_def(rd);
693 collector.reg_use(rn);
694 collector.reg_use(rm);
695 }
696 Inst::FpuRound { rd, rn, .. } => {
697 collector.reg_def(rd);
698 collector.reg_use(rn);
699 }
700 Inst::MovToFpu { rd, rn, .. } => {
701 collector.reg_def(rd);
702 collector.reg_use(rn);
703 }
704 Inst::FpuMoveFPImm { rd, .. } => {
705 collector.reg_def(rd);
706 }
707 Inst::MovToVec { rd, ri, rn, .. } => {
708 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
710 collector.reg_use(rn);
711 }
712 Inst::MovFromVec { rd, rn, .. } | Inst::MovFromVecSigned { rd, rn, .. } => {
713 collector.reg_def(rd);
714 collector.reg_use(rn);
715 }
716 Inst::VecDup { rd, rn, .. } => {
717 collector.reg_def(rd);
718 collector.reg_use(rn);
719 }
720 Inst::VecDupFromFpu { rd, rn, .. } => {
721 collector.reg_def(rd);
722 collector.reg_use(rn);
723 }
724 Inst::VecDupFPImm { rd, .. } => {
725 collector.reg_def(rd);
726 }
727 Inst::VecDupImm { rd, .. } => {
728 collector.reg_def(rd);
729 }
730 Inst::VecExtend { rd, rn, .. } => {
731 collector.reg_def(rd);
732 collector.reg_use(rn);
733 }
734 Inst::VecMovElement { rd, ri, rn, .. } => {
735 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
737 collector.reg_use(rn);
738 }
739 Inst::VecRRLong { rd, rn, .. } => {
740 collector.reg_def(rd);
741 collector.reg_use(rn);
742 }
743 Inst::VecRRNarrowLow { rd, rn, .. } => {
744 collector.reg_use(rn);
745 collector.reg_def(rd);
746 }
747 Inst::VecRRNarrowHigh { rd, ri, rn, .. } => {
748 collector.reg_use(rn);
749 collector.reg_reuse_def(rd, 2); collector.reg_use(ri);
751 }
752 Inst::VecRRPair { rd, rn, .. } => {
753 collector.reg_def(rd);
754 collector.reg_use(rn);
755 }
756 Inst::VecRRRLong { rd, rn, rm, .. } => {
757 collector.reg_def(rd);
758 collector.reg_use(rn);
759 collector.reg_use(rm);
760 }
761 Inst::VecRRRLongMod { rd, ri, rn, rm, .. } => {
762 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
764 collector.reg_use(rn);
765 collector.reg_use(rm);
766 }
767 Inst::VecRRPairLong { rd, rn, .. } => {
768 collector.reg_def(rd);
769 collector.reg_use(rn);
770 }
771 Inst::VecRRR { rd, rn, rm, .. } => {
772 collector.reg_def(rd);
773 collector.reg_use(rn);
774 collector.reg_use(rm);
775 }
776 Inst::VecRRRMod { rd, ri, rn, rm, .. } | Inst::VecFmlaElem { rd, ri, rn, rm, .. } => {
777 collector.reg_reuse_def(rd, 1); collector.reg_use(ri);
779 collector.reg_use(rn);
780 collector.reg_use(rm);
781 }
782 Inst::MovToNZCV { rn } => {
783 collector.reg_use(rn);
784 }
785 Inst::MovFromNZCV { rd } => {
786 collector.reg_def(rd);
787 }
788 Inst::Extend { rd, rn, .. } => {
789 collector.reg_def(rd);
790 collector.reg_use(rn);
791 }
792 Inst::Args { args } => {
793 for ArgPair { vreg, preg } in args {
794 collector.reg_fixed_def(vreg, *preg);
795 }
796 }
797 Inst::Rets { rets } => {
798 for RetPair { vreg, preg } in rets {
799 collector.reg_fixed_use(vreg, *preg);
800 }
801 }
802 Inst::Ret { .. } | Inst::AuthenticatedRet { .. } => {}
803 Inst::Jump { .. } => {}
804 Inst::Call { info, .. } => {
805 let CallInfo { uses, defs, .. } = &mut **info;
806 for CallArgPair { vreg, preg } in uses {
807 collector.reg_fixed_use(vreg, *preg);
808 }
809 for CallRetPair { vreg, location } in defs {
810 match location {
811 RetLocation::Reg(preg, ..) => collector.reg_fixed_def(vreg, *preg),
812 RetLocation::Stack(..) => collector.any_def(vreg),
813 }
814 }
815 collector.reg_clobbers(info.clobbers);
816 if let Some(try_call_info) = &mut info.try_call_info {
817 try_call_info.collect_operands(collector);
818 }
819 }
820 Inst::CallInd { info, .. } => {
821 let CallInfo {
822 dest, uses, defs, ..
823 } = &mut **info;
824 collector.reg_use(dest);
825 for CallArgPair { vreg, preg } in uses {
826 collector.reg_fixed_use(vreg, *preg);
827 }
828 for CallRetPair { vreg, location } in defs {
829 match location {
830 RetLocation::Reg(preg, ..) => collector.reg_fixed_def(vreg, *preg),
831 RetLocation::Stack(..) => collector.any_def(vreg),
832 }
833 }
834 collector.reg_clobbers(info.clobbers);
835 if let Some(try_call_info) = &mut info.try_call_info {
836 try_call_info.collect_operands(collector);
837 }
838 }
839 Inst::ReturnCall { info } => {
840 for CallArgPair { vreg, preg } in &mut info.uses {
841 collector.reg_fixed_use(vreg, *preg);
842 }
843 }
844 Inst::ReturnCallInd { info } => {
845 collector.reg_fixed_use(&mut info.dest, xreg(1));
850 for CallArgPair { vreg, preg } in &mut info.uses {
851 collector.reg_fixed_use(vreg, *preg);
852 }
853 }
854 Inst::CondBr { kind, .. } => match kind {
855 CondBrKind::Zero(rt, _) | CondBrKind::NotZero(rt, _) => collector.reg_use(rt),
856 CondBrKind::Cond(_) => {}
857 },
858 Inst::TestBitAndBranch { rn, .. } => {
859 collector.reg_use(rn);
860 }
861 Inst::IndirectBr { rn, .. } => {
862 collector.reg_use(rn);
863 }
864 Inst::Nop0 | Inst::Nop4 => {}
865 Inst::Brk => {}
866 Inst::Udf { .. } => {}
867 Inst::TrapIf { kind, .. } => match kind {
868 CondBrKind::Zero(rt, _) | CondBrKind::NotZero(rt, _) => collector.reg_use(rt),
869 CondBrKind::Cond(_) => {}
870 },
871 Inst::Adr { rd, .. } | Inst::Adrp { rd, .. } => {
872 collector.reg_def(rd);
873 }
874 Inst::Word4 { .. } | Inst::Word8 { .. } => {}
875 Inst::JTSequence {
876 ridx, rtmp1, rtmp2, ..
877 } => {
878 collector.reg_use(ridx);
879 collector.reg_early_def(rtmp1);
880 collector.reg_early_def(rtmp2);
881 }
882 Inst::LoadExtNameGot { rd, .. }
883 | Inst::LoadExtNameNear { rd, .. }
884 | Inst::LoadExtNameFar { rd, .. } => {
885 collector.reg_def(rd);
886 }
887 Inst::LoadAddr { rd, mem } => {
888 collector.reg_def(rd);
889 memarg_operands(mem, collector);
890 }
891 Inst::Paci { .. } | Inst::Xpaclri => {
892 }
895 Inst::Bti { .. } => {}
896
897 Inst::ElfTlsGetAddr { rd, tmp, .. } => {
898 collector.reg_fixed_def(rd, regs::xreg(0));
905 collector.reg_early_def(tmp);
906 }
907 Inst::MachOTlsGetAddr { rd, .. } => {
908 collector.reg_fixed_def(rd, regs::xreg(0));
909 let mut clobbers =
910 AArch64MachineDeps::get_regs_clobbered_by_call(CallConv::AppleAarch64, false);
911 clobbers.remove(regs::xreg_preg(0));
912 collector.reg_clobbers(clobbers);
913 }
914 Inst::Unwind { .. } => {}
915 Inst::EmitIsland { .. } => {}
916 Inst::DummyUse { reg } => {
917 collector.reg_use(reg);
918 }
919 Inst::LabelAddress { dst, .. } => {
920 collector.reg_def(dst);
921 }
922 Inst::SequencePoint { .. } => {}
923 Inst::StackProbeLoop { start, end, .. } => {
924 collector.reg_early_def(start);
925 collector.reg_use(end);
926 }
927 }
928}
929
930impl MachInst for Inst {
934 type ABIMachineSpec = AArch64MachineDeps;
935 type LabelUse = LabelUse;
936
937 const TRAP_OPCODE: &'static [u8] = &0xc11f_u32.to_le_bytes();
940
941 fn get_operands(&mut self, collector: &mut impl OperandVisitor) {
942 aarch64_get_operands(self, collector);
943 }
944
945 fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
946 match self {
947 &Inst::Mov {
948 size: OperandSize::Size64,
949 rd,
950 rm,
951 } => Some((rd, rm)),
952 &Inst::FpuMove64 { rd, rn } => Some((rd, rn)),
953 &Inst::FpuMove128 { rd, rn } => Some((rd, rn)),
954 _ => None,
955 }
956 }
957
958 fn is_included_in_clobbers(&self) -> bool {
959 let (caller, callee, is_exception) = match self {
960 Inst::Args { .. } => return false,
961 Inst::Call { info } => (
962 info.caller_conv,
963 info.callee_conv,
964 info.try_call_info.is_some(),
965 ),
966 Inst::CallInd { info } => (
967 info.caller_conv,
968 info.callee_conv,
969 info.try_call_info.is_some(),
970 ),
971 _ => return true,
972 };
973
974 let caller_clobbers = AArch64MachineDeps::get_regs_clobbered_by_call(caller, false);
986 let callee_clobbers = AArch64MachineDeps::get_regs_clobbered_by_call(callee, is_exception);
987
988 let mut all_clobbers = caller_clobbers;
989 all_clobbers.union_from(callee_clobbers);
990 all_clobbers != caller_clobbers
991 }
992
993 fn is_trap(&self) -> bool {
994 match self {
995 Self::Udf { .. } => true,
996 _ => false,
997 }
998 }
999
1000 fn is_args(&self) -> bool {
1001 match self {
1002 Self::Args { .. } => true,
1003 _ => false,
1004 }
1005 }
1006
1007 fn call_type(&self) -> CallType {
1008 match self {
1009 Inst::Call { .. }
1010 | Inst::CallInd { .. }
1011 | Inst::ElfTlsGetAddr { .. }
1012 | Inst::MachOTlsGetAddr { .. } => CallType::Regular,
1013
1014 Inst::ReturnCall { .. } | Inst::ReturnCallInd { .. } => CallType::TailCall,
1015
1016 _ => CallType::None,
1017 }
1018 }
1019
1020 fn is_term(&self) -> MachTerminator {
1021 match self {
1022 &Inst::Rets { .. } => MachTerminator::Ret,
1023 &Inst::ReturnCall { .. } | &Inst::ReturnCallInd { .. } => MachTerminator::RetCall,
1024 &Inst::Jump { .. } => MachTerminator::Branch,
1025 &Inst::CondBr { .. } => MachTerminator::Branch,
1026 &Inst::TestBitAndBranch { .. } => MachTerminator::Branch,
1027 &Inst::IndirectBr { .. } => MachTerminator::Branch,
1028 &Inst::JTSequence { .. } => MachTerminator::Branch,
1029 &Inst::Call { ref info } if info.try_call_info.is_some() => MachTerminator::Branch,
1030 &Inst::CallInd { ref info } if info.try_call_info.is_some() => MachTerminator::Branch,
1031 _ => MachTerminator::None,
1032 }
1033 }
1034
1035 fn is_mem_access(&self) -> bool {
1036 match self {
1037 &Inst::ULoad8 { .. }
1038 | &Inst::SLoad8 { .. }
1039 | &Inst::ULoad16 { .. }
1040 | &Inst::SLoad16 { .. }
1041 | &Inst::ULoad32 { .. }
1042 | &Inst::SLoad32 { .. }
1043 | &Inst::ULoad64 { .. }
1044 | &Inst::LoadP64 { .. }
1045 | &Inst::FpuLoad16 { .. }
1046 | &Inst::FpuLoad32 { .. }
1047 | &Inst::FpuLoad64 { .. }
1048 | &Inst::FpuLoad128 { .. }
1049 | &Inst::FpuLoadP64 { .. }
1050 | &Inst::FpuLoadP128 { .. }
1051 | &Inst::Store8 { .. }
1052 | &Inst::Store16 { .. }
1053 | &Inst::Store32 { .. }
1054 | &Inst::Store64 { .. }
1055 | &Inst::StoreP64 { .. }
1056 | &Inst::FpuStore16 { .. }
1057 | &Inst::FpuStore32 { .. }
1058 | &Inst::FpuStore64 { .. }
1059 | &Inst::FpuStore128 { .. } => true,
1060 _ => false,
1062 }
1063 }
1064
1065 fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
1066 let bits = ty.bits();
1067
1068 assert!(bits <= 128);
1069 assert!(to_reg.to_reg().class() == from_reg.class());
1070 match from_reg.class() {
1071 RegClass::Int => Inst::Mov {
1072 size: OperandSize::Size64,
1073 rd: to_reg,
1074 rm: from_reg,
1075 },
1076 RegClass::Float => {
1077 if bits > 64 {
1078 Inst::FpuMove128 {
1079 rd: to_reg,
1080 rn: from_reg,
1081 }
1082 } else {
1083 Inst::FpuMove64 {
1084 rd: to_reg,
1085 rn: from_reg,
1086 }
1087 }
1088 }
1089 RegClass::Vector => unreachable!(),
1090 }
1091 }
1092
1093 fn is_safepoint(&self) -> bool {
1094 match self {
1095 Inst::Call { .. } | Inst::CallInd { .. } => true,
1096 _ => false,
1097 }
1098 }
1099
1100 fn gen_dummy_use(reg: Reg) -> Inst {
1101 Inst::DummyUse { reg }
1102 }
1103
1104 fn gen_nop(preferred_size: usize) -> Inst {
1105 if preferred_size == 0 {
1106 return Inst::Nop0;
1107 }
1108 assert!(preferred_size >= 4);
1110 Inst::Nop4
1111 }
1112
1113 fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
1114 match ty {
1115 I8 => Ok((&[RegClass::Int], &[I8])),
1116 I16 => Ok((&[RegClass::Int], &[I16])),
1117 I32 => Ok((&[RegClass::Int], &[I32])),
1118 I64 => Ok((&[RegClass::Int], &[I64])),
1119 F16 => Ok((&[RegClass::Float], &[F16])),
1120 F32 => Ok((&[RegClass::Float], &[F32])),
1121 F64 => Ok((&[RegClass::Float], &[F64])),
1122 F128 => Ok((&[RegClass::Float], &[F128])),
1123 I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
1124 _ if ty.is_vector() && ty.bits() <= 128 => {
1125 let types = &[types::I8X2, types::I8X4, types::I8X8, types::I8X16];
1126 Ok((
1127 &[RegClass::Float],
1128 slice::from_ref(&types[ty.bytes().ilog2() as usize - 1]),
1129 ))
1130 }
1131 _ if ty.is_dynamic_vector() => Ok((&[RegClass::Float], &[I8X16])),
1132 _ => Err(CodegenError::Unsupported(format!(
1133 "Unexpected SSA-value type: {ty}"
1134 ))),
1135 }
1136 }
1137
1138 fn canonical_type_for_rc(rc: RegClass) -> Type {
1139 match rc {
1140 RegClass::Float => types::I8X16,
1141 RegClass::Int => types::I64,
1142 RegClass::Vector => unreachable!(),
1143 }
1144 }
1145
1146 fn gen_jump(target: MachLabel) -> Inst {
1147 Inst::Jump {
1148 dest: BranchTarget::Label(target),
1149 }
1150 }
1151
1152 fn worst_case_size() -> CodeOffset {
1153 44
1161 }
1162
1163 fn ref_type_regclass(_: &settings::Flags) -> RegClass {
1164 RegClass::Int
1165 }
1166
1167 fn gen_block_start(
1168 is_indirect_branch_target: bool,
1169 is_forward_edge_cfi_enabled: bool,
1170 ) -> Option<Self> {
1171 if is_indirect_branch_target && is_forward_edge_cfi_enabled {
1172 Some(Inst::Bti {
1173 targets: BranchTargetType::J,
1174 })
1175 } else {
1176 None
1177 }
1178 }
1179
1180 fn function_alignment() -> FunctionAlignment {
1181 FunctionAlignment {
1184 minimum: 4,
1185 preferred: 32,
1186 }
1187 }
1188}
1189
1190fn mem_finalize_for_show(mem: &AMode, access_ty: Type, state: &EmitState) -> (String, String) {
1194 let (mem_insts, mem) = mem_finalize(None, mem, access_ty, state);
1195 let mut mem_str = mem_insts
1196 .into_iter()
1197 .map(|inst| inst.print_with_state(&mut EmitState::default()))
1198 .collect::<Vec<_>>()
1199 .join(" ; ");
1200 if !mem_str.is_empty() {
1201 mem_str += " ; ";
1202 }
1203
1204 let mem = mem.pretty_print(access_ty.bytes() as u8);
1205 (mem_str, mem)
1206}
1207
1208fn pretty_print_try_call(info: &TryCallInfo) -> String {
1209 format!(
1210 "; b {:?}; catch [{}]",
1211 info.continuation,
1212 info.pretty_print_dests()
1213 )
1214}
1215
1216impl Inst {
1217 fn print_with_state(&self, state: &mut EmitState) -> String {
1218 fn op_name(alu_op: ALUOp) -> &'static str {
1219 match alu_op {
1220 ALUOp::Add => "add",
1221 ALUOp::Sub => "sub",
1222 ALUOp::Orr => "orr",
1223 ALUOp::And => "and",
1224 ALUOp::AndS => "ands",
1225 ALUOp::Eor => "eor",
1226 ALUOp::AddS => "adds",
1227 ALUOp::SubS => "subs",
1228 ALUOp::SMulH => "smulh",
1229 ALUOp::UMulH => "umulh",
1230 ALUOp::SDiv => "sdiv",
1231 ALUOp::UDiv => "udiv",
1232 ALUOp::AndNot => "bic",
1233 ALUOp::OrrNot => "orn",
1234 ALUOp::EorNot => "eon",
1235 ALUOp::Extr => "extr",
1236 ALUOp::Lsr => "lsr",
1237 ALUOp::Asr => "asr",
1238 ALUOp::Lsl => "lsl",
1239 ALUOp::Adc => "adc",
1240 ALUOp::AdcS => "adcs",
1241 ALUOp::Sbc => "sbc",
1242 ALUOp::SbcS => "sbcs",
1243 }
1244 }
1245
1246 match self {
1247 &Inst::Nop0 => "nop-zero-len".to_string(),
1248 &Inst::Nop4 => "nop".to_string(),
1249 &Inst::AluRRR {
1250 alu_op,
1251 size,
1252 rd,
1253 rn,
1254 rm,
1255 } => {
1256 let op = op_name(alu_op);
1257 let rd = pretty_print_ireg(rd.to_reg(), size);
1258 let rn = pretty_print_ireg(rn, size);
1259 let rm = pretty_print_ireg(rm, size);
1260 format!("{op} {rd}, {rn}, {rm}")
1261 }
1262 &Inst::AluRRRR {
1263 alu_op,
1264 size,
1265 rd,
1266 rn,
1267 rm,
1268 ra,
1269 } => {
1270 let (op, da_size) = match alu_op {
1271 ALUOp3::MAdd => ("madd", size),
1272 ALUOp3::MSub => ("msub", size),
1273 ALUOp3::UMAddL => ("umaddl", OperandSize::Size64),
1274 ALUOp3::SMAddL => ("smaddl", OperandSize::Size64),
1275 };
1276 let rd = pretty_print_ireg(rd.to_reg(), da_size);
1277 let rn = pretty_print_ireg(rn, size);
1278 let rm = pretty_print_ireg(rm, size);
1279 let ra = pretty_print_ireg(ra, da_size);
1280
1281 format!("{op} {rd}, {rn}, {rm}, {ra}")
1282 }
1283 &Inst::AluRRImm12 {
1284 alu_op,
1285 size,
1286 rd,
1287 rn,
1288 ref imm12,
1289 } => {
1290 let op = op_name(alu_op);
1291 let rd = pretty_print_ireg(rd.to_reg(), size);
1292 let rn = pretty_print_ireg(rn, size);
1293
1294 if imm12.bits == 0 && alu_op == ALUOp::Add && size.is64() {
1295 format!("mov {rd}, {rn}")
1297 } else {
1298 let imm12 = imm12.pretty_print(0);
1299 format!("{op} {rd}, {rn}, {imm12}")
1300 }
1301 }
1302 &Inst::AluRRImmLogic {
1303 alu_op,
1304 size,
1305 rd,
1306 rn,
1307 ref imml,
1308 } => {
1309 let op = op_name(alu_op);
1310 let rd = pretty_print_ireg(rd.to_reg(), size);
1311 let rn = pretty_print_ireg(rn, size);
1312 let imml = imml.pretty_print(0);
1313 format!("{op} {rd}, {rn}, {imml}")
1314 }
1315 &Inst::AluRRImmShift {
1316 alu_op,
1317 size,
1318 rd,
1319 rn,
1320 ref immshift,
1321 } => {
1322 let op = op_name(alu_op);
1323 let rd = pretty_print_ireg(rd.to_reg(), size);
1324 let rn = pretty_print_ireg(rn, size);
1325 let immshift = immshift.pretty_print(0);
1326 format!("{op} {rd}, {rn}, {immshift}")
1327 }
1328 &Inst::AluRRRShift {
1329 alu_op,
1330 size,
1331 rd,
1332 rn,
1333 rm,
1334 ref shiftop,
1335 } => {
1336 let op = op_name(alu_op);
1337 let rd = pretty_print_ireg(rd.to_reg(), size);
1338 let rn = pretty_print_ireg(rn, size);
1339 let rm = pretty_print_ireg(rm, size);
1340 let shiftop = shiftop.pretty_print(0);
1341 format!("{op} {rd}, {rn}, {rm}, {shiftop}")
1342 }
1343 &Inst::AluRRRExtend {
1344 alu_op,
1345 size,
1346 rd,
1347 rn,
1348 rm,
1349 ref extendop,
1350 } => {
1351 let op = op_name(alu_op);
1352 let rd = pretty_print_ireg(rd.to_reg(), size);
1353 let rn = pretty_print_ireg(rn, size);
1354 let rm = pretty_print_ireg(rm, size);
1355 let extendop = extendop.pretty_print(0);
1356 format!("{op} {rd}, {rn}, {rm}, {extendop}")
1357 }
1358 &Inst::BitRR { op, size, rd, rn } => {
1359 let op = op.op_str();
1360 let rd = pretty_print_ireg(rd.to_reg(), size);
1361 let rn = pretty_print_ireg(rn, size);
1362 format!("{op} {rd}, {rn}")
1363 }
1364 &Inst::ULoad8 { rd, ref mem, .. }
1365 | &Inst::SLoad8 { rd, ref mem, .. }
1366 | &Inst::ULoad16 { rd, ref mem, .. }
1367 | &Inst::SLoad16 { rd, ref mem, .. }
1368 | &Inst::ULoad32 { rd, ref mem, .. }
1369 | &Inst::SLoad32 { rd, ref mem, .. }
1370 | &Inst::ULoad64 { rd, ref mem, .. } => {
1371 let is_unscaled = match &mem {
1372 &AMode::Unscaled { .. } => true,
1373 _ => false,
1374 };
1375 let (op, size) = match (self, is_unscaled) {
1376 (&Inst::ULoad8 { .. }, false) => ("ldrb", OperandSize::Size32),
1377 (&Inst::ULoad8 { .. }, true) => ("ldurb", OperandSize::Size32),
1378 (&Inst::SLoad8 { .. }, false) => ("ldrsb", OperandSize::Size64),
1379 (&Inst::SLoad8 { .. }, true) => ("ldursb", OperandSize::Size64),
1380 (&Inst::ULoad16 { .. }, false) => ("ldrh", OperandSize::Size32),
1381 (&Inst::ULoad16 { .. }, true) => ("ldurh", OperandSize::Size32),
1382 (&Inst::SLoad16 { .. }, false) => ("ldrsh", OperandSize::Size64),
1383 (&Inst::SLoad16 { .. }, true) => ("ldursh", OperandSize::Size64),
1384 (&Inst::ULoad32 { .. }, false) => ("ldr", OperandSize::Size32),
1385 (&Inst::ULoad32 { .. }, true) => ("ldur", OperandSize::Size32),
1386 (&Inst::SLoad32 { .. }, false) => ("ldrsw", OperandSize::Size64),
1387 (&Inst::SLoad32 { .. }, true) => ("ldursw", OperandSize::Size64),
1388 (&Inst::ULoad64 { .. }, false) => ("ldr", OperandSize::Size64),
1389 (&Inst::ULoad64 { .. }, true) => ("ldur", OperandSize::Size64),
1390 _ => unreachable!(),
1391 };
1392
1393 let rd = pretty_print_ireg(rd.to_reg(), size);
1394 let mem = mem.clone();
1395 let access_ty = self.mem_type().unwrap();
1396 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1397
1398 format!("{mem_str}{op} {rd}, {mem}")
1399 }
1400 &Inst::Store8 { rd, ref mem, .. }
1401 | &Inst::Store16 { rd, ref mem, .. }
1402 | &Inst::Store32 { rd, ref mem, .. }
1403 | &Inst::Store64 { rd, ref mem, .. } => {
1404 let is_unscaled = match &mem {
1405 &AMode::Unscaled { .. } => true,
1406 _ => false,
1407 };
1408 let (op, size) = match (self, is_unscaled) {
1409 (&Inst::Store8 { .. }, false) => ("strb", OperandSize::Size32),
1410 (&Inst::Store8 { .. }, true) => ("sturb", OperandSize::Size32),
1411 (&Inst::Store16 { .. }, false) => ("strh", OperandSize::Size32),
1412 (&Inst::Store16 { .. }, true) => ("sturh", OperandSize::Size32),
1413 (&Inst::Store32 { .. }, false) => ("str", OperandSize::Size32),
1414 (&Inst::Store32 { .. }, true) => ("stur", OperandSize::Size32),
1415 (&Inst::Store64 { .. }, false) => ("str", OperandSize::Size64),
1416 (&Inst::Store64 { .. }, true) => ("stur", OperandSize::Size64),
1417 _ => unreachable!(),
1418 };
1419
1420 let rd = pretty_print_ireg(rd, size);
1421 let mem = mem.clone();
1422 let access_ty = self.mem_type().unwrap();
1423 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1424
1425 format!("{mem_str}{op} {rd}, {mem}")
1426 }
1427 &Inst::StoreP64 {
1428 rt, rt2, ref mem, ..
1429 } => {
1430 let rt = pretty_print_ireg(rt, OperandSize::Size64);
1431 let rt2 = pretty_print_ireg(rt2, OperandSize::Size64);
1432 let mem = mem.clone();
1433 let mem = mem.pretty_print_default();
1434 format!("stp {rt}, {rt2}, {mem}")
1435 }
1436 &Inst::LoadP64 {
1437 rt, rt2, ref mem, ..
1438 } => {
1439 let rt = pretty_print_ireg(rt.to_reg(), OperandSize::Size64);
1440 let rt2 = pretty_print_ireg(rt2.to_reg(), OperandSize::Size64);
1441 let mem = mem.clone();
1442 let mem = mem.pretty_print_default();
1443 format!("ldp {rt}, {rt2}, {mem}")
1444 }
1445 &Inst::Mov { size, rd, rm } => {
1446 let rd = pretty_print_ireg(rd.to_reg(), size);
1447 let rm = pretty_print_ireg(rm, size);
1448 format!("mov {rd}, {rm}")
1449 }
1450 &Inst::MovFromPReg { rd, rm } => {
1451 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1452 let rm = show_ireg_sized(rm.into(), OperandSize::Size64);
1453 format!("mov {rd}, {rm}")
1454 }
1455 &Inst::MovToPReg { rd, rm } => {
1456 let rd = show_ireg_sized(rd.into(), OperandSize::Size64);
1457 let rm = pretty_print_ireg(rm, OperandSize::Size64);
1458 format!("mov {rd}, {rm}")
1459 }
1460 &Inst::MovWide {
1461 op,
1462 rd,
1463 ref imm,
1464 size,
1465 } => {
1466 let op_str = match op {
1467 MoveWideOp::MovZ => "movz",
1468 MoveWideOp::MovN => "movn",
1469 };
1470 let rd = pretty_print_ireg(rd.to_reg(), size);
1471 let imm = imm.pretty_print(0);
1472 format!("{op_str} {rd}, {imm}")
1473 }
1474 &Inst::MovK {
1475 rd,
1476 rn,
1477 ref imm,
1478 size,
1479 } => {
1480 let rn = pretty_print_ireg(rn, size);
1481 let rd = pretty_print_ireg(rd.to_reg(), size);
1482 let imm = imm.pretty_print(0);
1483 format!("movk {rd}, {rn}, {imm}")
1484 }
1485 &Inst::CSel { rd, rn, rm, cond } => {
1486 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1487 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1488 let rm = pretty_print_ireg(rm, OperandSize::Size64);
1489 let cond = cond.pretty_print(0);
1490 format!("csel {rd}, {rn}, {rm}, {cond}")
1491 }
1492 &Inst::CSNeg { rd, rn, rm, cond } => {
1493 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1494 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1495 let rm = pretty_print_ireg(rm, OperandSize::Size64);
1496 let cond = cond.pretty_print(0);
1497 format!("csneg {rd}, {rn}, {rm}, {cond}")
1498 }
1499 &Inst::CSet { rd, cond } => {
1500 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1501 let cond = cond.pretty_print(0);
1502 format!("cset {rd}, {cond}")
1503 }
1504 &Inst::CSetm { rd, cond } => {
1505 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64);
1506 let cond = cond.pretty_print(0);
1507 format!("csetm {rd}, {cond}")
1508 }
1509 &Inst::CCmp {
1510 size,
1511 rn,
1512 rm,
1513 nzcv,
1514 cond,
1515 } => {
1516 let rn = pretty_print_ireg(rn, size);
1517 let rm = pretty_print_ireg(rm, size);
1518 let nzcv = nzcv.pretty_print(0);
1519 let cond = cond.pretty_print(0);
1520 format!("ccmp {rn}, {rm}, {nzcv}, {cond}")
1521 }
1522 &Inst::CCmpImm {
1523 size,
1524 rn,
1525 imm,
1526 nzcv,
1527 cond,
1528 } => {
1529 let rn = pretty_print_ireg(rn, size);
1530 let imm = imm.pretty_print(0);
1531 let nzcv = nzcv.pretty_print(0);
1532 let cond = cond.pretty_print(0);
1533 format!("ccmp {rn}, {imm}, {nzcv}, {cond}")
1534 }
1535 &Inst::AtomicRMW {
1536 rs, rt, rn, ty, op, ..
1537 } => {
1538 let op = match op {
1539 AtomicRMWOp::Add => "ldaddal",
1540 AtomicRMWOp::Clr => "ldclral",
1541 AtomicRMWOp::Eor => "ldeoral",
1542 AtomicRMWOp::Set => "ldsetal",
1543 AtomicRMWOp::Smax => "ldsmaxal",
1544 AtomicRMWOp::Umax => "ldumaxal",
1545 AtomicRMWOp::Smin => "ldsminal",
1546 AtomicRMWOp::Umin => "lduminal",
1547 AtomicRMWOp::Swp => "swpal",
1548 };
1549
1550 let size = OperandSize::from_ty(ty);
1551 let rs = pretty_print_ireg(rs, size);
1552 let rt = pretty_print_ireg(rt.to_reg(), size);
1553 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1554
1555 let ty_suffix = match ty {
1556 I8 => "b",
1557 I16 => "h",
1558 _ => "",
1559 };
1560 format!("{op}{ty_suffix} {rs}, {rt}, [{rn}]")
1561 }
1562 &Inst::AtomicRMWLoop {
1563 ty,
1564 op,
1565 addr,
1566 operand,
1567 oldval,
1568 scratch1,
1569 scratch2,
1570 ..
1571 } => {
1572 let op = match op {
1573 AtomicRMWLoopOp::Add => "add",
1574 AtomicRMWLoopOp::Sub => "sub",
1575 AtomicRMWLoopOp::Eor => "eor",
1576 AtomicRMWLoopOp::Orr => "orr",
1577 AtomicRMWLoopOp::And => "and",
1578 AtomicRMWLoopOp::Nand => "nand",
1579 AtomicRMWLoopOp::Smin => "smin",
1580 AtomicRMWLoopOp::Smax => "smax",
1581 AtomicRMWLoopOp::Umin => "umin",
1582 AtomicRMWLoopOp::Umax => "umax",
1583 AtomicRMWLoopOp::Xchg => "xchg",
1584 };
1585 let addr = pretty_print_ireg(addr, OperandSize::Size64);
1586 let operand = pretty_print_ireg(operand, OperandSize::Size64);
1587 let oldval = pretty_print_ireg(oldval.to_reg(), OperandSize::Size64);
1588 let scratch1 = pretty_print_ireg(scratch1.to_reg(), OperandSize::Size64);
1589 let scratch2 = pretty_print_ireg(scratch2.to_reg(), OperandSize::Size64);
1590 format!(
1591 "atomic_rmw_loop_{}_{} addr={} operand={} oldval={} scratch1={} scratch2={}",
1592 op,
1593 ty.bits(),
1594 addr,
1595 operand,
1596 oldval,
1597 scratch1,
1598 scratch2,
1599 )
1600 }
1601 &Inst::AtomicCAS {
1602 rd, rs, rt, rn, ty, ..
1603 } => {
1604 let op = match ty {
1605 I8 => "casalb",
1606 I16 => "casalh",
1607 I32 | I64 => "casal",
1608 _ => panic!("Unsupported type: {ty}"),
1609 };
1610 let size = OperandSize::from_ty(ty);
1611 let rd = pretty_print_ireg(rd.to_reg(), size);
1612 let rs = pretty_print_ireg(rs, size);
1613 let rt = pretty_print_ireg(rt, size);
1614 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1615
1616 format!("{op} {rd}, {rs}, {rt}, [{rn}]")
1617 }
1618 &Inst::AtomicCASLoop {
1619 ty,
1620 addr,
1621 expected,
1622 replacement,
1623 oldval,
1624 scratch,
1625 ..
1626 } => {
1627 let addr = pretty_print_ireg(addr, OperandSize::Size64);
1628 let expected = pretty_print_ireg(expected, OperandSize::Size64);
1629 let replacement = pretty_print_ireg(replacement, OperandSize::Size64);
1630 let oldval = pretty_print_ireg(oldval.to_reg(), OperandSize::Size64);
1631 let scratch = pretty_print_ireg(scratch.to_reg(), OperandSize::Size64);
1632 format!(
1633 "atomic_cas_loop_{} addr={}, expect={}, replacement={}, oldval={}, scratch={}",
1634 ty.bits(),
1635 addr,
1636 expected,
1637 replacement,
1638 oldval,
1639 scratch,
1640 )
1641 }
1642 &Inst::LoadAcquire {
1643 access_ty, rt, rn, ..
1644 } => {
1645 let (op, ty) = match access_ty {
1646 I8 => ("ldarb", I32),
1647 I16 => ("ldarh", I32),
1648 I32 => ("ldar", I32),
1649 I64 => ("ldar", I64),
1650 _ => panic!("Unsupported type: {access_ty}"),
1651 };
1652 let size = OperandSize::from_ty(ty);
1653 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1654 let rt = pretty_print_ireg(rt.to_reg(), size);
1655 format!("{op} {rt}, [{rn}]")
1656 }
1657 &Inst::StoreRelease {
1658 access_ty, rt, rn, ..
1659 } => {
1660 let (op, ty) = match access_ty {
1661 I8 => ("stlrb", I32),
1662 I16 => ("stlrh", I32),
1663 I32 => ("stlr", I32),
1664 I64 => ("stlr", I64),
1665 _ => panic!("Unsupported type: {access_ty}"),
1666 };
1667 let size = OperandSize::from_ty(ty);
1668 let rn = pretty_print_ireg(rn, OperandSize::Size64);
1669 let rt = pretty_print_ireg(rt, size);
1670 format!("{op} {rt}, [{rn}]")
1671 }
1672 &Inst::Fence {} => {
1673 format!("dmb ish")
1674 }
1675 &Inst::Csdb {} => {
1676 format!("csdb")
1677 }
1678 &Inst::FpuMove32 { rd, rn } => {
1679 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1680 let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size32);
1681 format!("fmov {rd}, {rn}")
1682 }
1683 &Inst::FpuMove64 { rd, rn } => {
1684 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1685 let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size64);
1686 format!("fmov {rd}, {rn}")
1687 }
1688 &Inst::FpuMove128 { rd, rn } => {
1689 let rd = pretty_print_reg(rd.to_reg());
1690 let rn = pretty_print_reg(rn);
1691 format!("mov {rd}.16b, {rn}.16b")
1692 }
1693 &Inst::FpuMoveFromVec { rd, rn, idx, size } => {
1694 let rd = pretty_print_vreg_scalar(rd.to_reg(), size.lane_size());
1695 let rn = pretty_print_vreg_element(rn, idx as usize, size.lane_size());
1696 format!("mov {rd}, {rn}")
1697 }
1698 &Inst::FpuExtend { rd, rn, size } => {
1699 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1700 let rn = pretty_print_vreg_scalar(rn, size);
1701 format!("fmov {rd}, {rn}")
1702 }
1703 &Inst::FpuRR {
1704 fpu_op,
1705 size,
1706 rd,
1707 rn,
1708 } => {
1709 let op = match fpu_op {
1710 FPUOp1::Abs => "fabs",
1711 FPUOp1::Neg => "fneg",
1712 FPUOp1::Sqrt => "fsqrt",
1713 FPUOp1::Cvt32To64 | FPUOp1::Cvt64To32 => "fcvt",
1714 };
1715 let dst_size = match fpu_op {
1716 FPUOp1::Cvt32To64 => ScalarSize::Size64,
1717 FPUOp1::Cvt64To32 => ScalarSize::Size32,
1718 _ => size,
1719 };
1720 let rd = pretty_print_vreg_scalar(rd.to_reg(), dst_size);
1721 let rn = pretty_print_vreg_scalar(rn, size);
1722 format!("{op} {rd}, {rn}")
1723 }
1724 &Inst::FpuRRR {
1725 fpu_op,
1726 size,
1727 rd,
1728 rn,
1729 rm,
1730 } => {
1731 let op = match fpu_op {
1732 FPUOp2::Add => "fadd",
1733 FPUOp2::Sub => "fsub",
1734 FPUOp2::Mul => "fmul",
1735 FPUOp2::Div => "fdiv",
1736 FPUOp2::Max => "fmax",
1737 FPUOp2::Min => "fmin",
1738 };
1739 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1740 let rn = pretty_print_vreg_scalar(rn, size);
1741 let rm = pretty_print_vreg_scalar(rm, size);
1742 format!("{op} {rd}, {rn}, {rm}")
1743 }
1744 &Inst::FpuRRI { fpu_op, rd, rn } => {
1745 let (op, imm, vector) = match fpu_op {
1746 FPUOpRI::UShr32(imm) => ("ushr", imm.pretty_print(0), true),
1747 FPUOpRI::UShr64(imm) => ("ushr", imm.pretty_print(0), false),
1748 };
1749
1750 let (rd, rn) = if vector {
1751 (
1752 pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size32x2),
1753 pretty_print_vreg_vector(rn, VectorSize::Size32x2),
1754 )
1755 } else {
1756 (
1757 pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64),
1758 pretty_print_vreg_scalar(rn, ScalarSize::Size64),
1759 )
1760 };
1761 format!("{op} {rd}, {rn}, {imm}")
1762 }
1763 &Inst::FpuRRIMod { fpu_op, rd, ri, rn } => {
1764 let (op, imm, vector) = match fpu_op {
1765 FPUOpRIMod::Sli32(imm) => ("sli", imm.pretty_print(0), true),
1766 FPUOpRIMod::Sli64(imm) => ("sli", imm.pretty_print(0), false),
1767 };
1768
1769 let (rd, ri, rn) = if vector {
1770 (
1771 pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size32x2),
1772 pretty_print_vreg_vector(ri, VectorSize::Size32x2),
1773 pretty_print_vreg_vector(rn, VectorSize::Size32x2),
1774 )
1775 } else {
1776 (
1777 pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64),
1778 pretty_print_vreg_scalar(ri, ScalarSize::Size64),
1779 pretty_print_vreg_scalar(rn, ScalarSize::Size64),
1780 )
1781 };
1782 format!("{op} {rd}, {ri}, {rn}, {imm}")
1783 }
1784 &Inst::FpuRRRR {
1785 fpu_op,
1786 size,
1787 rd,
1788 rn,
1789 rm,
1790 ra,
1791 } => {
1792 let op = match fpu_op {
1793 FPUOp3::MAdd => "fmadd",
1794 FPUOp3::MSub => "fmsub",
1795 FPUOp3::NMAdd => "fnmadd",
1796 FPUOp3::NMSub => "fnmsub",
1797 };
1798 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1799 let rn = pretty_print_vreg_scalar(rn, size);
1800 let rm = pretty_print_vreg_scalar(rm, size);
1801 let ra = pretty_print_vreg_scalar(ra, size);
1802 format!("{op} {rd}, {rn}, {rm}, {ra}")
1803 }
1804 &Inst::FpuCmp { size, rn, rm } => {
1805 let rn = pretty_print_vreg_scalar(rn, size);
1806 let rm = pretty_print_vreg_scalar(rm, size);
1807 format!("fcmp {rn}, {rm}")
1808 }
1809 &Inst::FpuLoad16 { rd, ref mem, .. } => {
1810 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size16);
1811 let mem = mem.clone();
1812 let access_ty = self.mem_type().unwrap();
1813 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1814 format!("{mem_str}ldr {rd}, {mem}")
1815 }
1816 &Inst::FpuLoad32 { rd, ref mem, .. } => {
1817 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1818 let mem = mem.clone();
1819 let access_ty = self.mem_type().unwrap();
1820 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1821 format!("{mem_str}ldr {rd}, {mem}")
1822 }
1823 &Inst::FpuLoad64 { rd, ref mem, .. } => {
1824 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1825 let mem = mem.clone();
1826 let access_ty = self.mem_type().unwrap();
1827 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1828 format!("{mem_str}ldr {rd}, {mem}")
1829 }
1830 &Inst::FpuLoad128 { rd, ref mem, .. } => {
1831 let rd = pretty_print_reg(rd.to_reg());
1832 let rd = "q".to_string() + &rd[1..];
1833 let mem = mem.clone();
1834 let access_ty = self.mem_type().unwrap();
1835 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1836 format!("{mem_str}ldr {rd}, {mem}")
1837 }
1838 &Inst::FpuStore16 { rd, ref mem, .. } => {
1839 let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size16);
1840 let mem = mem.clone();
1841 let access_ty = self.mem_type().unwrap();
1842 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1843 format!("{mem_str}str {rd}, {mem}")
1844 }
1845 &Inst::FpuStore32 { rd, ref mem, .. } => {
1846 let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size32);
1847 let mem = mem.clone();
1848 let access_ty = self.mem_type().unwrap();
1849 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1850 format!("{mem_str}str {rd}, {mem}")
1851 }
1852 &Inst::FpuStore64 { rd, ref mem, .. } => {
1853 let rd = pretty_print_vreg_scalar(rd, ScalarSize::Size64);
1854 let mem = mem.clone();
1855 let access_ty = self.mem_type().unwrap();
1856 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1857 format!("{mem_str}str {rd}, {mem}")
1858 }
1859 &Inst::FpuStore128 { rd, ref mem, .. } => {
1860 let rd = pretty_print_reg(rd);
1861 let rd = "q".to_string() + &rd[1..];
1862 let mem = mem.clone();
1863 let access_ty = self.mem_type().unwrap();
1864 let (mem_str, mem) = mem_finalize_for_show(&mem, access_ty, state);
1865 format!("{mem_str}str {rd}, {mem}")
1866 }
1867 &Inst::FpuLoadP64 {
1868 rt, rt2, ref mem, ..
1869 } => {
1870 let rt = pretty_print_vreg_scalar(rt.to_reg(), ScalarSize::Size64);
1871 let rt2 = pretty_print_vreg_scalar(rt2.to_reg(), ScalarSize::Size64);
1872 let mem = mem.clone();
1873 let mem = mem.pretty_print_default();
1874
1875 format!("ldp {rt}, {rt2}, {mem}")
1876 }
1877 &Inst::FpuStoreP64 {
1878 rt, rt2, ref mem, ..
1879 } => {
1880 let rt = pretty_print_vreg_scalar(rt, ScalarSize::Size64);
1881 let rt2 = pretty_print_vreg_scalar(rt2, ScalarSize::Size64);
1882 let mem = mem.clone();
1883 let mem = mem.pretty_print_default();
1884
1885 format!("stp {rt}, {rt2}, {mem}")
1886 }
1887 &Inst::FpuLoadP128 {
1888 rt, rt2, ref mem, ..
1889 } => {
1890 let rt = pretty_print_vreg_scalar(rt.to_reg(), ScalarSize::Size128);
1891 let rt2 = pretty_print_vreg_scalar(rt2.to_reg(), ScalarSize::Size128);
1892 let mem = mem.clone();
1893 let mem = mem.pretty_print_default();
1894
1895 format!("ldp {rt}, {rt2}, {mem}")
1896 }
1897 &Inst::FpuStoreP128 {
1898 rt, rt2, ref mem, ..
1899 } => {
1900 let rt = pretty_print_vreg_scalar(rt, ScalarSize::Size128);
1901 let rt2 = pretty_print_vreg_scalar(rt2, ScalarSize::Size128);
1902 let mem = mem.clone();
1903 let mem = mem.pretty_print_default();
1904
1905 format!("stp {rt}, {rt2}, {mem}")
1906 }
1907 &Inst::FpuToInt { op, rd, rn } => {
1908 let (op, sizesrc, sizedest) = match op {
1909 FpuToIntOp::F32ToI32 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size32),
1910 FpuToIntOp::F32ToU32 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size32),
1911 FpuToIntOp::F32ToI64 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size64),
1912 FpuToIntOp::F32ToU64 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size64),
1913 FpuToIntOp::F64ToI32 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size32),
1914 FpuToIntOp::F64ToU32 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size32),
1915 FpuToIntOp::F64ToI64 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size64),
1916 FpuToIntOp::F64ToU64 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size64),
1917 };
1918 let rd = pretty_print_ireg(rd.to_reg(), sizedest);
1919 let rn = pretty_print_vreg_scalar(rn, sizesrc);
1920 format!("{op} {rd}, {rn}")
1921 }
1922 &Inst::IntToFpu { op, rd, rn } => {
1923 let (op, sizesrc, sizedest) = match op {
1924 IntToFpuOp::I32ToF32 => ("scvtf", OperandSize::Size32, ScalarSize::Size32),
1925 IntToFpuOp::U32ToF32 => ("ucvtf", OperandSize::Size32, ScalarSize::Size32),
1926 IntToFpuOp::I64ToF32 => ("scvtf", OperandSize::Size64, ScalarSize::Size32),
1927 IntToFpuOp::U64ToF32 => ("ucvtf", OperandSize::Size64, ScalarSize::Size32),
1928 IntToFpuOp::I32ToF64 => ("scvtf", OperandSize::Size32, ScalarSize::Size64),
1929 IntToFpuOp::U32ToF64 => ("ucvtf", OperandSize::Size32, ScalarSize::Size64),
1930 IntToFpuOp::I64ToF64 => ("scvtf", OperandSize::Size64, ScalarSize::Size64),
1931 IntToFpuOp::U64ToF64 => ("ucvtf", OperandSize::Size64, ScalarSize::Size64),
1932 };
1933 let rd = pretty_print_vreg_scalar(rd.to_reg(), sizedest);
1934 let rn = pretty_print_ireg(rn, sizesrc);
1935 format!("{op} {rd}, {rn}")
1936 }
1937 &Inst::FpuCSel16 { rd, rn, rm, cond } => {
1938 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size16);
1939 let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size16);
1940 let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size16);
1941 let cond = cond.pretty_print(0);
1942 format!("fcsel {rd}, {rn}, {rm}, {cond}")
1943 }
1944 &Inst::FpuCSel32 { rd, rn, rm, cond } => {
1945 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size32);
1946 let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size32);
1947 let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size32);
1948 let cond = cond.pretty_print(0);
1949 format!("fcsel {rd}, {rn}, {rm}, {cond}")
1950 }
1951 &Inst::FpuCSel64 { rd, rn, rm, cond } => {
1952 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
1953 let rn = pretty_print_vreg_scalar(rn, ScalarSize::Size64);
1954 let rm = pretty_print_vreg_scalar(rm, ScalarSize::Size64);
1955 let cond = cond.pretty_print(0);
1956 format!("fcsel {rd}, {rn}, {rm}, {cond}")
1957 }
1958 &Inst::FpuRound { op, rd, rn } => {
1959 let (inst, size) = match op {
1960 FpuRoundMode::Minus32 => ("frintm", ScalarSize::Size32),
1961 FpuRoundMode::Minus64 => ("frintm", ScalarSize::Size64),
1962 FpuRoundMode::Plus32 => ("frintp", ScalarSize::Size32),
1963 FpuRoundMode::Plus64 => ("frintp", ScalarSize::Size64),
1964 FpuRoundMode::Zero32 => ("frintz", ScalarSize::Size32),
1965 FpuRoundMode::Zero64 => ("frintz", ScalarSize::Size64),
1966 FpuRoundMode::Nearest32 => ("frintn", ScalarSize::Size32),
1967 FpuRoundMode::Nearest64 => ("frintn", ScalarSize::Size64),
1968 };
1969 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1970 let rn = pretty_print_vreg_scalar(rn, size);
1971 format!("{inst} {rd}, {rn}")
1972 }
1973 &Inst::MovToFpu { rd, rn, size } => {
1974 let operand_size = size.operand_size();
1975 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1976 let rn = pretty_print_ireg(rn, operand_size);
1977 format!("fmov {rd}, {rn}")
1978 }
1979 &Inst::FpuMoveFPImm { rd, imm, size } => {
1980 let imm = imm.pretty_print(0);
1981 let rd = pretty_print_vreg_scalar(rd.to_reg(), size);
1982
1983 format!("fmov {rd}, {imm}")
1984 }
1985 &Inst::MovToVec {
1986 rd,
1987 ri,
1988 rn,
1989 idx,
1990 size,
1991 } => {
1992 let rd = pretty_print_vreg_element(rd.to_reg(), idx as usize, size.lane_size());
1993 let ri = pretty_print_vreg_element(ri, idx as usize, size.lane_size());
1994 let rn = pretty_print_ireg(rn, size.operand_size());
1995 format!("mov {rd}, {ri}, {rn}")
1996 }
1997 &Inst::MovFromVec { rd, rn, idx, size } => {
1998 let op = match size {
1999 ScalarSize::Size8 => "umov",
2000 ScalarSize::Size16 => "umov",
2001 ScalarSize::Size32 => "mov",
2002 ScalarSize::Size64 => "mov",
2003 _ => unimplemented!(),
2004 };
2005 let rd = pretty_print_ireg(rd.to_reg(), size.operand_size());
2006 let rn = pretty_print_vreg_element(rn, idx as usize, size);
2007 format!("{op} {rd}, {rn}")
2008 }
2009 &Inst::MovFromVecSigned {
2010 rd,
2011 rn,
2012 idx,
2013 size,
2014 scalar_size,
2015 } => {
2016 let rd = pretty_print_ireg(rd.to_reg(), scalar_size);
2017 let rn = pretty_print_vreg_element(rn, idx as usize, size.lane_size());
2018 format!("smov {rd}, {rn}")
2019 }
2020 &Inst::VecDup { rd, rn, size } => {
2021 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2022 let rn = pretty_print_ireg(rn, size.operand_size());
2023 format!("dup {rd}, {rn}")
2024 }
2025 &Inst::VecDupFromFpu { rd, rn, size, lane } => {
2026 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2027 let rn = pretty_print_vreg_element(rn, lane.into(), size.lane_size());
2028 format!("dup {rd}, {rn}")
2029 }
2030 &Inst::VecDupFPImm { rd, imm, size } => {
2031 let imm = imm.pretty_print(0);
2032 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2033
2034 format!("fmov {rd}, {imm}")
2035 }
2036 &Inst::VecDupImm {
2037 rd,
2038 imm,
2039 invert,
2040 size,
2041 } => {
2042 let imm = imm.pretty_print(0);
2043 let op = if invert { "mvni" } else { "movi" };
2044 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2045
2046 format!("{op} {rd}, {imm}")
2047 }
2048 &Inst::VecExtend {
2049 t,
2050 rd,
2051 rn,
2052 high_half,
2053 lane_size,
2054 } => {
2055 let vec64 = VectorSize::from_lane_size(lane_size.narrow(), false);
2056 let vec128 = VectorSize::from_lane_size(lane_size.narrow(), true);
2057 let rd_size = VectorSize::from_lane_size(lane_size, true);
2058 let (op, rn_size) = match (t, high_half) {
2059 (VecExtendOp::Sxtl, false) => ("sxtl", vec64),
2060 (VecExtendOp::Sxtl, true) => ("sxtl2", vec128),
2061 (VecExtendOp::Uxtl, false) => ("uxtl", vec64),
2062 (VecExtendOp::Uxtl, true) => ("uxtl2", vec128),
2063 };
2064 let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2065 let rn = pretty_print_vreg_vector(rn, rn_size);
2066 format!("{op} {rd}, {rn}")
2067 }
2068 &Inst::VecMovElement {
2069 rd,
2070 ri,
2071 rn,
2072 dest_idx,
2073 src_idx,
2074 size,
2075 } => {
2076 let rd =
2077 pretty_print_vreg_element(rd.to_reg(), dest_idx as usize, size.lane_size());
2078 let ri = pretty_print_vreg_element(ri, dest_idx as usize, size.lane_size());
2079 let rn = pretty_print_vreg_element(rn, src_idx as usize, size.lane_size());
2080 format!("mov {rd}, {ri}, {rn}")
2081 }
2082 &Inst::VecRRLong {
2083 op,
2084 rd,
2085 rn,
2086 high_half,
2087 } => {
2088 let (op, rd_size, size, suffix) = match (op, high_half) {
2089 (VecRRLongOp::Fcvtl16, false) => {
2090 ("fcvtl", VectorSize::Size32x4, VectorSize::Size16x4, "")
2091 }
2092 (VecRRLongOp::Fcvtl16, true) => {
2093 ("fcvtl2", VectorSize::Size32x4, VectorSize::Size16x8, "")
2094 }
2095 (VecRRLongOp::Fcvtl32, false) => {
2096 ("fcvtl", VectorSize::Size64x2, VectorSize::Size32x2, "")
2097 }
2098 (VecRRLongOp::Fcvtl32, true) => {
2099 ("fcvtl2", VectorSize::Size64x2, VectorSize::Size32x4, "")
2100 }
2101 (VecRRLongOp::Shll8, false) => {
2102 ("shll", VectorSize::Size16x8, VectorSize::Size8x8, ", #8")
2103 }
2104 (VecRRLongOp::Shll8, true) => {
2105 ("shll2", VectorSize::Size16x8, VectorSize::Size8x16, ", #8")
2106 }
2107 (VecRRLongOp::Shll16, false) => {
2108 ("shll", VectorSize::Size32x4, VectorSize::Size16x4, ", #16")
2109 }
2110 (VecRRLongOp::Shll16, true) => {
2111 ("shll2", VectorSize::Size32x4, VectorSize::Size16x8, ", #16")
2112 }
2113 (VecRRLongOp::Shll32, false) => {
2114 ("shll", VectorSize::Size64x2, VectorSize::Size32x2, ", #32")
2115 }
2116 (VecRRLongOp::Shll32, true) => {
2117 ("shll2", VectorSize::Size64x2, VectorSize::Size32x4, ", #32")
2118 }
2119 };
2120 let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2121 let rn = pretty_print_vreg_vector(rn, size);
2122
2123 format!("{op} {rd}, {rn}{suffix}")
2124 }
2125 &Inst::VecRRNarrowLow {
2126 op,
2127 rd,
2128 rn,
2129 lane_size,
2130 ..
2131 }
2132 | &Inst::VecRRNarrowHigh {
2133 op,
2134 rd,
2135 rn,
2136 lane_size,
2137 ..
2138 } => {
2139 let vec64 = VectorSize::from_lane_size(lane_size, false);
2140 let vec128 = VectorSize::from_lane_size(lane_size, true);
2141 let rn_size = VectorSize::from_lane_size(lane_size.widen(), true);
2142 let high_half = match self {
2143 &Inst::VecRRNarrowLow { .. } => false,
2144 &Inst::VecRRNarrowHigh { .. } => true,
2145 _ => unreachable!(),
2146 };
2147 let (op, rd_size) = match (op, high_half) {
2148 (VecRRNarrowOp::Xtn, false) => ("xtn", vec64),
2149 (VecRRNarrowOp::Xtn, true) => ("xtn2", vec128),
2150 (VecRRNarrowOp::Sqxtn, false) => ("sqxtn", vec64),
2151 (VecRRNarrowOp::Sqxtn, true) => ("sqxtn2", vec128),
2152 (VecRRNarrowOp::Sqxtun, false) => ("sqxtun", vec64),
2153 (VecRRNarrowOp::Sqxtun, true) => ("sqxtun2", vec128),
2154 (VecRRNarrowOp::Uqxtn, false) => ("uqxtn", vec64),
2155 (VecRRNarrowOp::Uqxtn, true) => ("uqxtn2", vec128),
2156 (VecRRNarrowOp::Fcvtn, false) => ("fcvtn", vec64),
2157 (VecRRNarrowOp::Fcvtn, true) => ("fcvtn2", vec128),
2158 };
2159 let rn = pretty_print_vreg_vector(rn, rn_size);
2160 let rd = pretty_print_vreg_vector(rd.to_reg(), rd_size);
2161 let ri = match self {
2162 &Inst::VecRRNarrowLow { .. } => "".to_string(),
2163 &Inst::VecRRNarrowHigh { ri, .. } => {
2164 format!("{}, ", pretty_print_vreg_vector(ri, rd_size))
2165 }
2166 _ => unreachable!(),
2167 };
2168
2169 format!("{op} {rd}, {ri}{rn}")
2170 }
2171 &Inst::VecRRPair { op, rd, rn } => {
2172 let op = match op {
2173 VecPairOp::Addp => "addp",
2174 };
2175 let rd = pretty_print_vreg_scalar(rd.to_reg(), ScalarSize::Size64);
2176 let rn = pretty_print_vreg_vector(rn, VectorSize::Size64x2);
2177
2178 format!("{op} {rd}, {rn}")
2179 }
2180 &Inst::VecRRPairLong { op, rd, rn } => {
2181 let (op, dest, src) = match op {
2182 VecRRPairLongOp::Saddlp8 => {
2183 ("saddlp", VectorSize::Size16x8, VectorSize::Size8x16)
2184 }
2185 VecRRPairLongOp::Saddlp16 => {
2186 ("saddlp", VectorSize::Size32x4, VectorSize::Size16x8)
2187 }
2188 VecRRPairLongOp::Uaddlp8 => {
2189 ("uaddlp", VectorSize::Size16x8, VectorSize::Size8x16)
2190 }
2191 VecRRPairLongOp::Uaddlp16 => {
2192 ("uaddlp", VectorSize::Size32x4, VectorSize::Size16x8)
2193 }
2194 };
2195 let rd = pretty_print_vreg_vector(rd.to_reg(), dest);
2196 let rn = pretty_print_vreg_vector(rn, src);
2197
2198 format!("{op} {rd}, {rn}")
2199 }
2200 &Inst::VecRRR {
2201 rd,
2202 rn,
2203 rm,
2204 alu_op,
2205 size,
2206 } => {
2207 let (op, size) = match alu_op {
2208 VecALUOp::Sqadd => ("sqadd", size),
2209 VecALUOp::Uqadd => ("uqadd", size),
2210 VecALUOp::Sqsub => ("sqsub", size),
2211 VecALUOp::Uqsub => ("uqsub", size),
2212 VecALUOp::Cmeq => ("cmeq", size),
2213 VecALUOp::Cmge => ("cmge", size),
2214 VecALUOp::Cmgt => ("cmgt", size),
2215 VecALUOp::Cmhs => ("cmhs", size),
2216 VecALUOp::Cmhi => ("cmhi", size),
2217 VecALUOp::Fcmeq => ("fcmeq", size),
2218 VecALUOp::Fcmgt => ("fcmgt", size),
2219 VecALUOp::Fcmge => ("fcmge", size),
2220 VecALUOp::Umaxp => ("umaxp", size),
2221 VecALUOp::Add => ("add", size),
2222 VecALUOp::Sub => ("sub", size),
2223 VecALUOp::Mul => ("mul", size),
2224 VecALUOp::Sshl => ("sshl", size),
2225 VecALUOp::Ushl => ("ushl", size),
2226 VecALUOp::Umin => ("umin", size),
2227 VecALUOp::Smin => ("smin", size),
2228 VecALUOp::Umax => ("umax", size),
2229 VecALUOp::Smax => ("smax", size),
2230 VecALUOp::Urhadd => ("urhadd", size),
2231 VecALUOp::Fadd => ("fadd", size),
2232 VecALUOp::Fsub => ("fsub", size),
2233 VecALUOp::Fdiv => ("fdiv", size),
2234 VecALUOp::Fmax => ("fmax", size),
2235 VecALUOp::Fmin => ("fmin", size),
2236 VecALUOp::Fmul => ("fmul", size),
2237 VecALUOp::Addp => ("addp", size),
2238 VecALUOp::Zip1 => ("zip1", size),
2239 VecALUOp::Zip2 => ("zip2", size),
2240 VecALUOp::Sqrdmulh => ("sqrdmulh", size),
2241 VecALUOp::Uzp1 => ("uzp1", size),
2242 VecALUOp::Uzp2 => ("uzp2", size),
2243 VecALUOp::Trn1 => ("trn1", size),
2244 VecALUOp::Trn2 => ("trn2", size),
2245
2246 VecALUOp::And => ("and", size.as_scalar8_vector()),
2249 VecALUOp::Bic => ("bic", size.as_scalar8_vector()),
2250 VecALUOp::Orr => ("orr", size.as_scalar8_vector()),
2251 VecALUOp::Orn => ("orn", size.as_scalar8_vector()),
2252 VecALUOp::Eor => ("eor", size.as_scalar8_vector()),
2253 };
2254 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2255 let rn = pretty_print_vreg_vector(rn, size);
2256 let rm = pretty_print_vreg_vector(rm, size);
2257 format!("{op} {rd}, {rn}, {rm}")
2258 }
2259 &Inst::VecRRRMod {
2260 rd,
2261 ri,
2262 rn,
2263 rm,
2264 alu_op,
2265 size,
2266 } => {
2267 let (op, size) = match alu_op {
2268 VecALUModOp::Bsl => ("bsl", VectorSize::Size8x16),
2269 VecALUModOp::Fmla => ("fmla", size),
2270 VecALUModOp::Fmls => ("fmls", size),
2271 };
2272 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2273 let ri = pretty_print_vreg_vector(ri, size);
2274 let rn = pretty_print_vreg_vector(rn, size);
2275 let rm = pretty_print_vreg_vector(rm, size);
2276 format!("{op} {rd}, {ri}, {rn}, {rm}")
2277 }
2278 &Inst::VecFmlaElem {
2279 rd,
2280 ri,
2281 rn,
2282 rm,
2283 alu_op,
2284 size,
2285 idx,
2286 } => {
2287 let (op, size) = match alu_op {
2288 VecALUModOp::Fmla => ("fmla", size),
2289 VecALUModOp::Fmls => ("fmls", size),
2290 _ => unreachable!(),
2291 };
2292 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2293 let ri = pretty_print_vreg_vector(ri, size);
2294 let rn = pretty_print_vreg_vector(rn, size);
2295 let rm = pretty_print_vreg_element(rm, idx.into(), size.lane_size());
2296 format!("{op} {rd}, {ri}, {rn}, {rm}")
2297 }
2298 &Inst::VecRRRLong {
2299 rd,
2300 rn,
2301 rm,
2302 alu_op,
2303 high_half,
2304 } => {
2305 let (op, dest_size, src_size) = match (alu_op, high_half) {
2306 (VecRRRLongOp::Smull8, false) => {
2307 ("smull", VectorSize::Size16x8, VectorSize::Size8x8)
2308 }
2309 (VecRRRLongOp::Smull8, true) => {
2310 ("smull2", VectorSize::Size16x8, VectorSize::Size8x16)
2311 }
2312 (VecRRRLongOp::Smull16, false) => {
2313 ("smull", VectorSize::Size32x4, VectorSize::Size16x4)
2314 }
2315 (VecRRRLongOp::Smull16, true) => {
2316 ("smull2", VectorSize::Size32x4, VectorSize::Size16x8)
2317 }
2318 (VecRRRLongOp::Smull32, false) => {
2319 ("smull", VectorSize::Size64x2, VectorSize::Size32x2)
2320 }
2321 (VecRRRLongOp::Smull32, true) => {
2322 ("smull2", VectorSize::Size64x2, VectorSize::Size32x4)
2323 }
2324 (VecRRRLongOp::Umull8, false) => {
2325 ("umull", VectorSize::Size16x8, VectorSize::Size8x8)
2326 }
2327 (VecRRRLongOp::Umull8, true) => {
2328 ("umull2", VectorSize::Size16x8, VectorSize::Size8x16)
2329 }
2330 (VecRRRLongOp::Umull16, false) => {
2331 ("umull", VectorSize::Size32x4, VectorSize::Size16x4)
2332 }
2333 (VecRRRLongOp::Umull16, true) => {
2334 ("umull2", VectorSize::Size32x4, VectorSize::Size16x8)
2335 }
2336 (VecRRRLongOp::Umull32, false) => {
2337 ("umull", VectorSize::Size64x2, VectorSize::Size32x2)
2338 }
2339 (VecRRRLongOp::Umull32, true) => {
2340 ("umull2", VectorSize::Size64x2, VectorSize::Size32x4)
2341 }
2342 };
2343 let rd = pretty_print_vreg_vector(rd.to_reg(), dest_size);
2344 let rn = pretty_print_vreg_vector(rn, src_size);
2345 let rm = pretty_print_vreg_vector(rm, src_size);
2346 format!("{op} {rd}, {rn}, {rm}")
2347 }
2348 &Inst::VecRRRLongMod {
2349 rd,
2350 ri,
2351 rn,
2352 rm,
2353 alu_op,
2354 high_half,
2355 } => {
2356 let (op, dest_size, src_size) = match (alu_op, high_half) {
2357 (VecRRRLongModOp::Umlal8, false) => {
2358 ("umlal", VectorSize::Size16x8, VectorSize::Size8x8)
2359 }
2360 (VecRRRLongModOp::Umlal8, true) => {
2361 ("umlal2", VectorSize::Size16x8, VectorSize::Size8x16)
2362 }
2363 (VecRRRLongModOp::Umlal16, false) => {
2364 ("umlal", VectorSize::Size32x4, VectorSize::Size16x4)
2365 }
2366 (VecRRRLongModOp::Umlal16, true) => {
2367 ("umlal2", VectorSize::Size32x4, VectorSize::Size16x8)
2368 }
2369 (VecRRRLongModOp::Umlal32, false) => {
2370 ("umlal", VectorSize::Size64x2, VectorSize::Size32x2)
2371 }
2372 (VecRRRLongModOp::Umlal32, true) => {
2373 ("umlal2", VectorSize::Size64x2, VectorSize::Size32x4)
2374 }
2375 };
2376 let rd = pretty_print_vreg_vector(rd.to_reg(), dest_size);
2377 let ri = pretty_print_vreg_vector(ri, dest_size);
2378 let rn = pretty_print_vreg_vector(rn, src_size);
2379 let rm = pretty_print_vreg_vector(rm, src_size);
2380 format!("{op} {rd}, {ri}, {rn}, {rm}")
2381 }
2382 &Inst::VecMisc { op, rd, rn, size } => {
2383 let (op, size, suffix) = match op {
2384 VecMisc2::Neg => ("neg", size, ""),
2385 VecMisc2::Abs => ("abs", size, ""),
2386 VecMisc2::Fabs => ("fabs", size, ""),
2387 VecMisc2::Fneg => ("fneg", size, ""),
2388 VecMisc2::Fsqrt => ("fsqrt", size, ""),
2389 VecMisc2::Rev16 => ("rev16", size, ""),
2390 VecMisc2::Rev32 => ("rev32", size, ""),
2391 VecMisc2::Rev64 => ("rev64", size, ""),
2392 VecMisc2::Fcvtzs => ("fcvtzs", size, ""),
2393 VecMisc2::Fcvtzu => ("fcvtzu", size, ""),
2394 VecMisc2::Scvtf => ("scvtf", size, ""),
2395 VecMisc2::Ucvtf => ("ucvtf", size, ""),
2396 VecMisc2::Frintn => ("frintn", size, ""),
2397 VecMisc2::Frintz => ("frintz", size, ""),
2398 VecMisc2::Frintm => ("frintm", size, ""),
2399 VecMisc2::Frintp => ("frintp", size, ""),
2400 VecMisc2::Cnt => ("cnt", size, ""),
2401 VecMisc2::Cmeq0 => ("cmeq", size, ", #0"),
2402 VecMisc2::Cmge0 => ("cmge", size, ", #0"),
2403 VecMisc2::Cmgt0 => ("cmgt", size, ", #0"),
2404 VecMisc2::Cmle0 => ("cmle", size, ", #0"),
2405 VecMisc2::Cmlt0 => ("cmlt", size, ", #0"),
2406 VecMisc2::Fcmeq0 => ("fcmeq", size, ", #0.0"),
2407 VecMisc2::Fcmge0 => ("fcmge", size, ", #0.0"),
2408 VecMisc2::Fcmgt0 => ("fcmgt", size, ", #0.0"),
2409 VecMisc2::Fcmle0 => ("fcmle", size, ", #0.0"),
2410 VecMisc2::Fcmlt0 => ("fcmlt", size, ", #0.0"),
2411
2412 VecMisc2::Not => ("mvn", size.as_scalar8_vector(), ""),
2415 };
2416 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2417 let rn = pretty_print_vreg_vector(rn, size);
2418 format!("{op} {rd}, {rn}{suffix}")
2419 }
2420 &Inst::VecLanes { op, rd, rn, size } => {
2421 let op = match op {
2422 VecLanesOp::Uminv => "uminv",
2423 VecLanesOp::Addv => "addv",
2424 };
2425 let rd = pretty_print_vreg_scalar(rd.to_reg(), size.lane_size());
2426 let rn = pretty_print_vreg_vector(rn, size);
2427 format!("{op} {rd}, {rn}")
2428 }
2429 &Inst::VecShiftImm {
2430 op,
2431 rd,
2432 rn,
2433 size,
2434 imm,
2435 } => {
2436 let op = match op {
2437 VecShiftImmOp::Shl => "shl",
2438 VecShiftImmOp::Ushr => "ushr",
2439 VecShiftImmOp::Sshr => "sshr",
2440 };
2441 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2442 let rn = pretty_print_vreg_vector(rn, size);
2443 format!("{op} {rd}, {rn}, #{imm}")
2444 }
2445 &Inst::VecShiftImmMod {
2446 op,
2447 rd,
2448 ri,
2449 rn,
2450 size,
2451 imm,
2452 } => {
2453 let op = match op {
2454 VecShiftImmModOp::Sli => "sli",
2455 };
2456 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2457 let ri = pretty_print_vreg_vector(ri, size);
2458 let rn = pretty_print_vreg_vector(rn, size);
2459 format!("{op} {rd}, {ri}, {rn}, #{imm}")
2460 }
2461 &Inst::VecExtract { rd, rn, rm, imm4 } => {
2462 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2463 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2464 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2465 format!("ext {rd}, {rn}, {rm}, #{imm4}")
2466 }
2467 &Inst::VecTbl { rd, rn, rm } => {
2468 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2469 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2470 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2471 format!("tbl {rd}, {{ {rn} }}, {rm}")
2472 }
2473 &Inst::VecTblExt { rd, ri, rn, rm } => {
2474 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2475 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2476 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2477 let ri = pretty_print_vreg_vector(ri, VectorSize::Size8x16);
2478 format!("tbx {rd}, {ri}, {{ {rn} }}, {rm}")
2479 }
2480 &Inst::VecTbl2 { rd, rn, rn2, rm } => {
2481 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2482 let rn2 = pretty_print_vreg_vector(rn2, VectorSize::Size8x16);
2483 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2484 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2485 format!("tbl {rd}, {{ {rn}, {rn2} }}, {rm}")
2486 }
2487 &Inst::VecTbl2Ext {
2488 rd,
2489 ri,
2490 rn,
2491 rn2,
2492 rm,
2493 } => {
2494 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2495 let rn2 = pretty_print_vreg_vector(rn2, VectorSize::Size8x16);
2496 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2497 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2498 let ri = pretty_print_vreg_vector(ri, VectorSize::Size8x16);
2499 format!("tbx {rd}, {ri}, {{ {rn}, {rn2} }}, {rm}")
2500 }
2501 &Inst::VecLoadReplicate { rd, rn, size, .. } => {
2502 let rd = pretty_print_vreg_vector(rd.to_reg(), size);
2503 let rn = pretty_print_reg(rn);
2504
2505 format!("ld1r {{ {rd} }}, [{rn}]")
2506 }
2507 &Inst::VecCSel { rd, rn, rm, cond } => {
2508 let rd = pretty_print_vreg_vector(rd.to_reg(), VectorSize::Size8x16);
2509 let rn = pretty_print_vreg_vector(rn, VectorSize::Size8x16);
2510 let rm = pretty_print_vreg_vector(rm, VectorSize::Size8x16);
2511 let cond = cond.pretty_print(0);
2512 format!("vcsel {rd}, {rn}, {rm}, {cond} (if-then-else diamond)")
2513 }
2514 &Inst::MovToNZCV { rn } => {
2515 let rn = pretty_print_reg(rn);
2516 format!("msr nzcv, {rn}")
2517 }
2518 &Inst::MovFromNZCV { rd } => {
2519 let rd = pretty_print_reg(rd.to_reg());
2520 format!("mrs {rd}, nzcv")
2521 }
2522 &Inst::Extend {
2523 rd,
2524 rn,
2525 signed: false,
2526 from_bits: 1,
2527 ..
2528 } => {
2529 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size32);
2530 let rn = pretty_print_ireg(rn, OperandSize::Size32);
2531 format!("and {rd}, {rn}, #1")
2532 }
2533 &Inst::Extend {
2534 rd,
2535 rn,
2536 signed: false,
2537 from_bits: 32,
2538 to_bits: 64,
2539 } => {
2540 let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size32);
2544 let rn = pretty_print_ireg(rn, OperandSize::Size32);
2545 format!("mov {rd}, {rn}")
2546 }
2547 &Inst::Extend {
2548 rd,
2549 rn,
2550 signed,
2551 from_bits,
2552 to_bits,
2553 } => {
2554 assert!(from_bits <= to_bits);
2555 let op = match (signed, from_bits) {
2556 (false, 8) => "uxtb",
2557 (true, 8) => "sxtb",
2558 (false, 16) => "uxth",
2559 (true, 16) => "sxth",
2560 (true, 32) => "sxtw",
2561 (true, _) => "sbfx",
2562 (false, _) => "ubfx",
2563 };
2564 if op == "sbfx" || op == "ubfx" {
2565 let dest_size = OperandSize::from_bits(to_bits);
2566 let rd = pretty_print_ireg(rd.to_reg(), dest_size);
2567 let rn = pretty_print_ireg(rn, dest_size);
2568 format!("{op} {rd}, {rn}, #0, #{from_bits}")
2569 } else {
2570 let dest_size = if signed {
2571 OperandSize::from_bits(to_bits)
2572 } else {
2573 OperandSize::Size32
2574 };
2575 let rd = pretty_print_ireg(rd.to_reg(), dest_size);
2576 let rn = pretty_print_ireg(rn, OperandSize::from_bits(from_bits));
2577 format!("{op} {rd}, {rn}")
2578 }
2579 }
2580 &Inst::Call { ref info } => {
2581 let try_call = info
2582 .try_call_info
2583 .as_ref()
2584 .map(|tci| pretty_print_try_call(tci))
2585 .unwrap_or_default();
2586 format!("bl 0{try_call}")
2587 }
2588 &Inst::CallInd { ref info } => {
2589 let rn = pretty_print_reg(info.dest);
2590 let try_call = info
2591 .try_call_info
2592 .as_ref()
2593 .map(|tci| pretty_print_try_call(tci))
2594 .unwrap_or_default();
2595 format!("blr {rn}{try_call}")
2596 }
2597 &Inst::ReturnCall { ref info } => {
2598 let mut s = format!(
2599 "return_call {:?} new_stack_arg_size:{}",
2600 info.dest, info.new_stack_arg_size
2601 );
2602 for ret in &info.uses {
2603 let preg = pretty_print_reg(ret.preg);
2604 let vreg = pretty_print_reg(ret.vreg);
2605 write!(&mut s, " {vreg}={preg}").unwrap();
2606 }
2607 s
2608 }
2609 &Inst::ReturnCallInd { ref info } => {
2610 let callee = pretty_print_reg(info.dest);
2611 let mut s = format!(
2612 "return_call_ind {callee} new_stack_arg_size:{}",
2613 info.new_stack_arg_size
2614 );
2615 for ret in &info.uses {
2616 let preg = pretty_print_reg(ret.preg);
2617 let vreg = pretty_print_reg(ret.vreg);
2618 write!(&mut s, " {vreg}={preg}").unwrap();
2619 }
2620 s
2621 }
2622 &Inst::Args { ref args } => {
2623 let mut s = "args".to_string();
2624 for arg in args {
2625 let preg = pretty_print_reg(arg.preg);
2626 let def = pretty_print_reg(arg.vreg.to_reg());
2627 write!(&mut s, " {def}={preg}").unwrap();
2628 }
2629 s
2630 }
2631 &Inst::Rets { ref rets } => {
2632 let mut s = "rets".to_string();
2633 for ret in rets {
2634 let preg = pretty_print_reg(ret.preg);
2635 let vreg = pretty_print_reg(ret.vreg);
2636 write!(&mut s, " {vreg}={preg}").unwrap();
2637 }
2638 s
2639 }
2640 &Inst::Ret {} => "ret".to_string(),
2641 &Inst::AuthenticatedRet { key, is_hint } => {
2642 let key = match key {
2643 APIKey::AZ => "az",
2644 APIKey::BZ => "bz",
2645 APIKey::ASP => "asp",
2646 APIKey::BSP => "bsp",
2647 };
2648 match is_hint {
2649 false => format!("reta{key}"),
2650 true => format!("auti{key} ; ret"),
2651 }
2652 }
2653 &Inst::Jump { ref dest } => {
2654 let dest = dest.pretty_print(0);
2655 format!("b {dest}")
2656 }
2657 &Inst::CondBr {
2658 ref taken,
2659 ref not_taken,
2660 ref kind,
2661 } => {
2662 let taken = taken.pretty_print(0);
2663 let not_taken = not_taken.pretty_print(0);
2664 match kind {
2665 &CondBrKind::Zero(reg, size) => {
2666 let reg = pretty_print_reg_sized(reg, size);
2667 format!("cbz {reg}, {taken} ; b {not_taken}")
2668 }
2669 &CondBrKind::NotZero(reg, size) => {
2670 let reg = pretty_print_reg_sized(reg, size);
2671 format!("cbnz {reg}, {taken} ; b {not_taken}")
2672 }
2673 &CondBrKind::Cond(c) => {
2674 let c = c.pretty_print(0);
2675 format!("b.{c} {taken} ; b {not_taken}")
2676 }
2677 }
2678 }
2679 &Inst::TestBitAndBranch {
2680 kind,
2681 ref taken,
2682 ref not_taken,
2683 rn,
2684 bit,
2685 } => {
2686 let cond = match kind {
2687 TestBitAndBranchKind::Z => "z",
2688 TestBitAndBranchKind::NZ => "nz",
2689 };
2690 let taken = taken.pretty_print(0);
2691 let not_taken = not_taken.pretty_print(0);
2692 let rn = pretty_print_reg(rn);
2693 format!("tb{cond} {rn}, #{bit}, {taken} ; b {not_taken}")
2694 }
2695 &Inst::IndirectBr { rn, .. } => {
2696 let rn = pretty_print_reg(rn);
2697 format!("br {rn}")
2698 }
2699 &Inst::Brk => "brk #0xf000".to_string(),
2700 &Inst::Udf { .. } => "udf #0xc11f".to_string(),
2701 &Inst::TrapIf {
2702 ref kind,
2703 trap_code,
2704 } => match kind {
2705 &CondBrKind::Zero(reg, size) => {
2706 let reg = pretty_print_reg_sized(reg, size);
2707 format!("cbz {reg}, #trap={trap_code}")
2708 }
2709 &CondBrKind::NotZero(reg, size) => {
2710 let reg = pretty_print_reg_sized(reg, size);
2711 format!("cbnz {reg}, #trap={trap_code}")
2712 }
2713 &CondBrKind::Cond(c) => {
2714 let c = c.pretty_print(0);
2715 format!("b.{c} #trap={trap_code}")
2716 }
2717 },
2718 &Inst::Adr { rd, off } => {
2719 let rd = pretty_print_reg(rd.to_reg());
2720 format!("adr {rd}, pc+{off}")
2721 }
2722 &Inst::Adrp { rd, off } => {
2723 let rd = pretty_print_reg(rd.to_reg());
2724 let byte_offset = off * 4096;
2726 format!("adrp {rd}, pc+{byte_offset}")
2727 }
2728 &Inst::Word4 { data } => format!("data.i32 {data}"),
2729 &Inst::Word8 { data } => format!("data.i64 {data}"),
2730 &Inst::JTSequence {
2731 default,
2732 ref targets,
2733 ridx,
2734 rtmp1,
2735 rtmp2,
2736 ..
2737 } => {
2738 let ridx = pretty_print_reg(ridx);
2739 let rtmp1 = pretty_print_reg(rtmp1.to_reg());
2740 let rtmp2 = pretty_print_reg(rtmp2.to_reg());
2741 let default_target = BranchTarget::Label(default).pretty_print(0);
2742 format!(
2743 concat!(
2744 "b.hs {} ; ",
2745 "csel {}, xzr, {}, hs ; ",
2746 "csdb ; ",
2747 "adr {}, pc+16 ; ",
2748 "ldrsw {}, [{}, {}, uxtw #2] ; ",
2749 "add {}, {}, {} ; ",
2750 "br {} ; ",
2751 "jt_entries {:?}"
2752 ),
2753 default_target,
2754 rtmp2,
2755 ridx,
2756 rtmp1,
2757 rtmp2,
2758 rtmp1,
2759 rtmp2,
2760 rtmp1,
2761 rtmp1,
2762 rtmp2,
2763 rtmp1,
2764 targets
2765 )
2766 }
2767 &Inst::LoadExtNameGot { rd, ref name } => {
2768 let rd = pretty_print_reg(rd.to_reg());
2769 format!("load_ext_name_got {rd}, {name:?}")
2770 }
2771 &Inst::LoadExtNameNear {
2772 rd,
2773 ref name,
2774 offset,
2775 } => {
2776 let rd = pretty_print_reg(rd.to_reg());
2777 format!("load_ext_name_near {rd}, {name:?}+{offset}")
2778 }
2779 &Inst::LoadExtNameFar {
2780 rd,
2781 ref name,
2782 offset,
2783 } => {
2784 let rd = pretty_print_reg(rd.to_reg());
2785 format!("load_ext_name_far {rd}, {name:?}+{offset}")
2786 }
2787 &Inst::LoadAddr { rd, ref mem } => {
2788 let mem = mem.clone();
2793 let (mem_insts, mem) = mem_finalize(None, &mem, I8, state);
2794 let mut ret = String::new();
2795 for inst in mem_insts.into_iter() {
2796 ret.push_str(&inst.print_with_state(&mut EmitState::default()));
2797 }
2798 let (reg, index_reg, offset) = match mem {
2799 AMode::RegExtended { rn, rm, extendop } => (rn, Some((rm, extendop)), 0),
2800 AMode::Unscaled { rn, simm9 } => (rn, None, simm9.value()),
2801 AMode::UnsignedOffset { rn, uimm12 } => (rn, None, uimm12.value() as i32),
2802 _ => panic!("Unsupported case for LoadAddr: {mem:?}"),
2803 };
2804 let abs_offset = if offset < 0 {
2805 -offset as u64
2806 } else {
2807 offset as u64
2808 };
2809 let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
2810
2811 if let Some((idx, extendop)) = index_reg {
2812 let add = Inst::AluRRRExtend {
2813 alu_op: ALUOp::Add,
2814 size: OperandSize::Size64,
2815 rd,
2816 rn: reg,
2817 rm: idx,
2818 extendop,
2819 };
2820
2821 ret.push_str(&add.print_with_state(&mut EmitState::default()));
2822 } else if offset == 0 {
2823 let mov = Inst::gen_move(rd, reg, I64);
2824 ret.push_str(&mov.print_with_state(&mut EmitState::default()));
2825 } else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
2826 let add = Inst::AluRRImm12 {
2827 alu_op,
2828 size: OperandSize::Size64,
2829 rd,
2830 rn: reg,
2831 imm12,
2832 };
2833 ret.push_str(&add.print_with_state(&mut EmitState::default()));
2834 } else {
2835 let tmp = writable_spilltmp_reg();
2836 for inst in Inst::load_constant(tmp, abs_offset).into_iter() {
2837 ret.push_str(&inst.print_with_state(&mut EmitState::default()));
2838 }
2839 let add = Inst::AluRRR {
2840 alu_op,
2841 size: OperandSize::Size64,
2842 rd,
2843 rn: reg,
2844 rm: tmp.to_reg(),
2845 };
2846 ret.push_str(&add.print_with_state(&mut EmitState::default()));
2847 }
2848 ret
2849 }
2850 &Inst::Paci { key } => {
2851 let key = match key {
2852 APIKey::AZ => "az",
2853 APIKey::BZ => "bz",
2854 APIKey::ASP => "asp",
2855 APIKey::BSP => "bsp",
2856 };
2857
2858 "paci".to_string() + key
2859 }
2860 &Inst::Xpaclri => "xpaclri".to_string(),
2861 &Inst::Bti { targets } => {
2862 let targets = match targets {
2863 BranchTargetType::None => "",
2864 BranchTargetType::C => " c",
2865 BranchTargetType::J => " j",
2866 BranchTargetType::JC => " jc",
2867 };
2868
2869 "bti".to_string() + targets
2870 }
2871 &Inst::EmitIsland { needed_space } => format!("emit_island {needed_space}"),
2872
2873 &Inst::ElfTlsGetAddr {
2874 ref symbol,
2875 rd,
2876 tmp,
2877 } => {
2878 let rd = pretty_print_reg(rd.to_reg());
2879 let tmp = pretty_print_reg(tmp.to_reg());
2880 format!("elf_tls_get_addr {}, {}, {}", rd, tmp, symbol.display(None))
2881 }
2882 &Inst::MachOTlsGetAddr { ref symbol, rd } => {
2883 let rd = pretty_print_reg(rd.to_reg());
2884 format!("macho_tls_get_addr {}, {}", rd, symbol.display(None))
2885 }
2886 &Inst::Unwind { ref inst } => {
2887 format!("unwind {inst:?}")
2888 }
2889 &Inst::DummyUse { reg } => {
2890 let reg = pretty_print_reg(reg);
2891 format!("dummy_use {reg}")
2892 }
2893 &Inst::LabelAddress { dst, label } => {
2894 let dst = pretty_print_reg(dst.to_reg());
2895 format!("label_address {dst}, {label:?}")
2896 }
2897 &Inst::SequencePoint {} => {
2898 format!("sequence_point")
2899 }
2900 &Inst::StackProbeLoop { start, end, step } => {
2901 let start = pretty_print_reg(start.to_reg());
2902 let end = pretty_print_reg(end);
2903 let step = step.pretty_print(0);
2904 format!("stack_probe_loop {start}, {end}, {step}")
2905 }
2906 }
2907 }
2908}
2909
2910#[derive(Clone, Copy, Debug, PartialEq, Eq)]
2915pub enum LabelUse {
2916 Branch14,
2919 Branch19,
2922 Branch26,
2925 Ldr19,
2928 Adr21,
2931 PCRel32,
2934}
2935
2936impl MachInstLabelUse for LabelUse {
2937 const ALIGN: CodeOffset = 4;
2939
2940 fn max_pos_range(self) -> CodeOffset {
2942 match self {
2943 LabelUse::Branch14 => (1 << 15) - 1,
2947 LabelUse::Branch19 => (1 << 20) - 1,
2948 LabelUse::Branch26 => (1 << 27) - 1,
2949 LabelUse::Ldr19 => (1 << 20) - 1,
2950 LabelUse::Adr21 => (1 << 20) - 1,
2953 LabelUse::PCRel32 => 0x7fffffff,
2954 }
2955 }
2956
2957 fn max_neg_range(self) -> CodeOffset {
2959 self.max_pos_range() + 1
2962 }
2963
2964 fn patch_size(self) -> CodeOffset {
2966 4
2968 }
2969
2970 fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
2972 let pc_rel = (label_offset as i64) - (use_offset as i64);
2973 debug_assert!(pc_rel <= self.max_pos_range() as i64);
2974 debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
2975 let pc_rel = pc_rel as u32;
2976 let insn_word = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
2977 let mask = match self {
2978 LabelUse::Branch14 => 0x0007ffe0, LabelUse::Branch19 => 0x00ffffe0, LabelUse::Branch26 => 0x03ffffff, LabelUse::Ldr19 => 0x00ffffe0, LabelUse::Adr21 => 0x60ffffe0, LabelUse::PCRel32 => 0xffffffff,
2984 };
2985 let pc_rel_shifted = match self {
2986 LabelUse::Adr21 | LabelUse::PCRel32 => pc_rel,
2987 _ => {
2988 debug_assert!(pc_rel & 3 == 0);
2989 pc_rel >> 2
2990 }
2991 };
2992 let pc_rel_inserted = match self {
2993 LabelUse::Branch14 => (pc_rel_shifted & 0x3fff) << 5,
2994 LabelUse::Branch19 | LabelUse::Ldr19 => (pc_rel_shifted & 0x7ffff) << 5,
2995 LabelUse::Branch26 => pc_rel_shifted & 0x3ffffff,
2996 LabelUse::Adr21 => (pc_rel_shifted & 0x1ffffc) << 3 | (pc_rel_shifted & 3) << 29,
2999 LabelUse::PCRel32 => pc_rel_shifted,
3000 };
3001 let is_add = match self {
3002 LabelUse::PCRel32 => true,
3003 _ => false,
3004 };
3005 let insn_word = if is_add {
3006 insn_word.wrapping_add(pc_rel_inserted)
3007 } else {
3008 (insn_word & !mask) | pc_rel_inserted
3009 };
3010 buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
3011 }
3012
3013 fn supports_veneer(self) -> bool {
3015 match self {
3016 LabelUse::Branch14 | LabelUse::Branch19 => true, LabelUse::Branch26 => true, _ => false,
3019 }
3020 }
3021
3022 fn veneer_size(self) -> CodeOffset {
3024 match self {
3025 LabelUse::Branch14 | LabelUse::Branch19 => 4,
3026 LabelUse::Branch26 => 20,
3027 _ => unreachable!(),
3028 }
3029 }
3030
3031 fn worst_case_veneer_size() -> CodeOffset {
3032 20
3033 }
3034
3035 fn generate_veneer(
3038 self,
3039 buffer: &mut [u8],
3040 veneer_offset: CodeOffset,
3041 ) -> (CodeOffset, LabelUse) {
3042 match self {
3043 LabelUse::Branch14 | LabelUse::Branch19 => {
3044 let insn_word = 0b000101 << 26;
3047 buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
3048 (veneer_offset, LabelUse::Branch26)
3049 }
3050
3051 LabelUse::Branch26 => {
3062 let tmp1 = regs::spilltmp_reg();
3063 let tmp1_w = regs::writable_spilltmp_reg();
3064 let tmp2 = regs::tmp2_reg();
3065 let tmp2_w = regs::writable_tmp2_reg();
3066 let ldr = emit::enc_ldst_imm19(0b1001_1000, 16 / 4, tmp1);
3068 let adr = emit::enc_adr(12, tmp2_w);
3070 let add = emit::enc_arith_rrr(0b10001011_000, 0, tmp1_w, tmp1, tmp2);
3072 let br = emit::enc_br(tmp1);
3074 buffer[0..4].clone_from_slice(&u32::to_le_bytes(ldr));
3075 buffer[4..8].clone_from_slice(&u32::to_le_bytes(adr));
3076 buffer[8..12].clone_from_slice(&u32::to_le_bytes(add));
3077 buffer[12..16].clone_from_slice(&u32::to_le_bytes(br));
3078 (veneer_offset + 16, LabelUse::PCRel32)
3081 }
3082
3083 _ => panic!("Unsupported label-reference type for veneer generation!"),
3084 }
3085 }
3086
3087 fn from_reloc(reloc: Reloc, addend: Addend) -> Option<LabelUse> {
3088 match (reloc, addend) {
3089 (Reloc::Arm64Call, 0) => Some(LabelUse::Branch26),
3090 _ => None,
3091 }
3092 }
3093}
3094
3095#[cfg(test)]
3096mod tests {
3097 use super::*;
3098
3099 #[test]
3100 fn inst_size_test() {
3101 let expected = if cfg!(target_pointer_width = "32") && !cfg!(target_arch = "arm") {
3104 28
3105 } else {
3106 32
3107 };
3108 assert_eq!(expected, std::mem::size_of::<Inst>());
3109 }
3110}