cranelift_assembler_x64/
lib.rs

1//! A Cranelift-specific x64 assembler.
2//!
3//! All instructions known to this assembler are listed in the [`inst`] module.
4//! The [`Inst`] enumeration contains a variant for each, allowing matching over
5//! all these instructions. All of this is parameterized by a [`Registers`]
6//! trait, allowing users of this assembler to plug in their own register types.
7//!
8//! ```
9//! # use cranelift_assembler_x64::{Feature, Imm8, inst, Inst, Registers};
10//! // Tell the assembler the type of registers we're using; we can always
11//! // encode a HW register as a `u8` (e.g., `eax = 0`).
12//! pub struct Regs;
13//! impl Registers for Regs {
14//!     type ReadGpr = u8;
15//!     type ReadWriteGpr = u8;
16//!     type ReadXmm = u8;
17//!     type ReadWriteXmm = u8;
18//! }
19//!
20//! // Then, build one of the `AND` instructions; this one operates on an
21//! // implicit `AL` register with an immediate. We can collect a sequence of
22//! // instructions by converting to the `Inst` type.
23//! let and = inst::andb_i::new(Imm8::new(0b10101010));
24//! let seq: Vec<Inst<Regs>> = vec![and.into()];
25//!
26//! // Now we can encode this sequence into a code buffer, checking that each
27//! // instruction is valid in 64-bit mode.
28//! let mut buffer = vec![];
29//! let offsets = vec![];
30//! for inst in seq {
31//!     if inst.features().contains(&Feature::_64b) {
32//!         inst.encode(&mut buffer, &offsets);
33//!     }
34//! }
35//! assert_eq!(buffer, vec![0x24, 0b10101010]);
36//! ```
37//!
38//! With an [`Inst`], we can encode the instruction into a code buffer; see the
39//! [example](Inst).
40
41#![allow(
42    non_camel_case_types,
43    reason = "all of the generated struct names use snake case"
44)]
45
46mod api;
47pub mod gpr;
48mod imm;
49pub mod inst;
50mod mem;
51mod rex;
52pub mod xmm;
53
54#[cfg(any(test, feature = "fuzz"))]
55pub mod fuzz;
56
57/// An assembly instruction; contains all instructions known to the assembler.
58///
59/// This wraps all [`inst`] structures into a single enumeration for collecting
60/// instructions.
61#[doc(inline)]
62// This re-exports, and documents, a module that is more convenient to use at
63// the library top-level.
64pub use inst::Inst;
65
66/// A CPU feature.
67///
68/// This is generated from the `dsl::Feature` enumeration defined in the `meta`
69/// crate (i.e., an exact replica). It describes the CPUID features required by
70/// an instruction; see [`Inst::features`].
71#[doc(inline)]
72// Like `Inst` above, a convenient re-export.
73pub use inst::Feature;
74
75pub use api::{
76    AsReg, CodeSink, Constant, KnownOffset, KnownOffsetTable, Label, RegisterVisitor, Registers,
77    TrapCode,
78};
79pub use gpr::{Gpr, NonRspGpr, Size};
80pub use imm::{Extension, Imm16, Imm32, Imm8, Simm16, Simm32, Simm8};
81pub use mem::{
82    Amode, AmodeOffset, AmodeOffsetPlusKnownOffset, DeferredTarget, GprMem, Scale, XmmMem,
83};
84pub use rex::RexFlags;
85pub use xmm::Xmm;
86
87/// List the files generated to create this assembler.
88pub fn generated_files() -> Vec<std::path::PathBuf> {
89    include!(concat!(env!("OUT_DIR"), "/generated-files.rs"))
90}
cranelift_assembler_x64/lib.rs

cranelift_assembler_x64/
lib.rs
