cranelift_assembler_x64

Module inst

Source
Expand description

Expose all known instructions as Rust structs; this is generated in build.rs.

See also: Inst, an enum containing all these instructions.

Structsยง

adcb_i
adcb: I(al[rw], imm8) => 0x14 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcb_mi
adcb: MI(rm8[rw], imm8) => 0x80 /2 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcb_mr
adcb: MR(rm8[rw], r8) => 0x10 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcb_rm
adcb: RM(r8[rw], rm8) => 0x12 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcl_i
adcl: I(eax[rw], imm32) => 0x15 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcl_mi
adcl: MI(rm32[rw], imm32) => 0x81 /2 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcl_mi_sxb
adcl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /2 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcl_mr
adcl: MR(rm32[rw], r32) => 0x11 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcl_rm
adcl: RM(r32[rw], rm32) => 0x13 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcq_i_sxl
adcq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x15 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcq_mi_sxb
adcq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /2 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcq_mi_sxl
adcq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /2 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcq_mr
adcq: MR(rm64[rw], r64) => REX.W + 0x11 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcq_rm
adcq: RM(r64[rw], rm64) => REX.W + 0x13 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcw_i
adcw: I(ax[rw], imm16) => 0x66 + 0x15 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcw_mi
adcw: MI(rm16[rw], imm16) => 0x66 + 0x81 /2 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcw_mr
adcw: MR(rm16[rw], r16) => 0x66 + 0x11 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
adcw_rm
adcw: RM(r16[rw], rm16) => 0x66 + 0x13 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addb_i
addb: I(al[rw], imm8) => 0x04 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addb_mi
addb: MI(rm8[rw], imm8) => 0x80 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addb_mr
addb: MR(rm8[rw], r8) => 0x00 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addb_rm
addb: RM(r8[rw], rm8) => 0x02 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addl_i
addl: I(eax[rw], imm32) => 0x05 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addl_mi
addl: MI(rm32[rw], imm32) => 0x81 /0 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addl_mi_sxb
addl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addl_mr
addl: MR(rm32[rw], r32) => 0x01 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addl_rm
addl: RM(r32[rw], rm32) => 0x03 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addpd_a
addpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x58 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addps_a
addps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x58 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addq_i_sxl
addq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x05 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addq_mi_sxb
addq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /0 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addq_mi_sxl
addq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /0 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addq_mr
addq: MR(rm64[rw], r64) => REX.W + 0x01 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addq_rm
addq: RM(r64[rw], rm64) => REX.W + 0x03 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addsd_a
addsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x58 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addss_a
addss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x58 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addw_i
addw: I(ax[rw], imm16) => 0x66 + 0x05 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addw_mi
addw: MI(rm16[rw], imm16) => 0x66 + 0x81 /0 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addw_mr
addw: MR(rm16[rw], r16) => 0x66 + 0x01 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
addw_rm
addw: RM(r16[rw], rm16) => 0x66 + 0x03 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andb_i
andb: I(al[rw], imm8) => 0x24 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andb_mi
andb: MI(rm8[rw], imm8) => 0x80 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andb_mr
andb: MR(rm8[rw], r8) => 0x20 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andb_rm
andb: RM(r8[rw], rm8) => 0x22 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andl_i
andl: I(eax[rw], imm32) => 0x25 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andl_mi
andl: MI(rm32[rw], imm32) => 0x81 /4 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andl_mi_sxb
andl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andl_mr
andl: MR(rm32[rw], r32) => 0x21 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andl_rm
andl: RM(r32[rw], rm32) => 0x23 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andnpd_a
andnpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x55 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andnps_a
andnps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x55 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andpd_a
andpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x54 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andps_a
andps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x54 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andq_i_sxl
andq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x25 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andq_mi_sxb
andq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /4 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andq_mi_sxl
andq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /4 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andq_mr
andq: MR(rm64[rw], r64) => REX.W + 0x21 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andq_rm
andq: RM(r64[rw], rm64) => REX.W + 0x23 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andw_i
andw: I(ax[rw], imm16) => 0x66 + 0x25 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andw_mi
andw: MI(rm16[rw], imm16) => 0x66 + 0x81 /4 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andw_mr
andw: MR(rm16[rw], r16) => 0x66 + 0x21 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
andw_rm
andw: RM(r16[rw], rm16) => 0x66 + 0x23 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsfl_rm
bsfl: RM(r32[w], rm32) => 0x0F + 0xBC /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsfq_rm
bsfq: RM(r64[w], rm64) => REX.W + 0x0F + 0xBC /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsfw_rm
bsfw: RM(r16[w], rm16) => 0x66 + 0x0F + 0xBC /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsrl_rm
bsrl: RM(r32[w], rm32) => 0x0F + 0xBD /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsrq_rm
bsrq: RM(r64[w], rm64) => REX.W + 0x0F + 0xBD /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bsrw_rm
bsrw: RM(r16[w], rm16) => 0x66 + 0x0F + 0xBD /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bswapl_o
bswapl: O(r32[rw]) => 0x0F + 0xC8 +rd [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
bswapq_o
bswapq: O(r64[rw]) => REX.W + 0x0F + 0xC8 +ro [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cbtw_zo
cbtw: ZO(ax[rw,implicit]) => 0x66 + 0x98 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cltd_zo
cltd: ZO(edx[w,implicit], eax[implicit]) => 0x99 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cltq_zo
cltq: ZO(rax[rw,implicit]) => REX.W + 0x98 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cqto_zo
cqto: ZO(rdx[w,implicit], rax[implicit]) => REX.W + 0x99 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtdq2pd_a
cvtdq2pd: A(xmm1[w], xmm_m64) => 0xF3 + 0x0F + 0xE6 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtdq2ps_a
cvtdq2ps: A(xmm1[w], xmm_m128[align]) => 0x0F + 0x5B /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtpd2ps_a
cvtpd2ps: A(xmm1[w], xmm_m128[align]) => 0x66 + 0x0F + 0x5A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtps2pd_a
cvtps2pd: A(xmm1[w], xmm_m64) => 0x0F + 0x5A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsd2si_a
cvtsd2si: A(r32[w], xmm_m64) => 0xF2 + 0x0F + 0x2D /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsd2si_aq
cvtsd2si: AQ(r64[w], xmm_m64) => 0xF2 + REX.W + 0x0F + 0x2D /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsd2ss_a
cvtsd2ss: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x5A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsi2sdl_a
cvtsi2sdl: A(xmm1[rw], rm32) => 0xF2 + 0x0F + 0x2A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsi2sdq_a
cvtsi2sdq: A(xmm1[rw], rm64) => 0xF2 + REX.W + 0x0F + 0x2A /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsi2ssl_a
cvtsi2ssl: A(xmm1[rw], rm32) => 0xF3 + 0x0F + 0x2A /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtsi2ssq_a
cvtsi2ssq: A(xmm1[rw], rm64) => 0xF3 + REX.W + 0x0F + 0x2A /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtss2sd_a
cvtss2sd: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x5A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtss2si_a
cvtss2si: A(r32[w], xmm_m32) => 0xF3 + 0x0F + 0x2D /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvtss2si_aq
cvtss2si: AQ(r64[w], xmm_m32) => 0xF3 + REX.W + 0x0F + 0x2D /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttpd2dq_a
cvttpd2dq: A(xmm1[w], xmm_m128[align]) => 0x66 + 0x0F + 0xE6 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttps2dq_a
cvttps2dq: A(xmm1[w], xmm_m128[align]) => 0xF3 + 0x0F + 0x5B /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttsd2si_a
cvttsd2si: A(r32[w], xmm_m64) => 0xF2 + 0x0F + 0x2C /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttsd2si_aq
cvttsd2si: AQ(r64[w], xmm_m64) => 0xF2 + REX.W + 0x0F + 0x2C /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttss2si_a
cvttss2si: A(r32[w], xmm_m32) => 0xF3 + 0x0F + 0x2C /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cvttss2si_aq
cvttss2si: AQ(r64[w], xmm_m32) => 0xF3 + REX.W + 0x0F + 0x2C /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cwtd_zo
cwtd: ZO(dx[w,implicit], ax[implicit]) => 0x66 + 0x99 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
cwtl_zo
cwtl: ZO(eax[rw,implicit]) => 0x98 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
divb_m
divb: M(ax[rw,implicit], rm8) => 0xF6 /6 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
divl_m
divl: M(eax[rw,implicit], edx[rw,implicit], rm32) => 0xF7 /6 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
divq_m
divq: M(rax[rw,implicit], rdx[rw,implicit], rm64) => REX.W + 0xF7 /6 [_64b] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
divw_m
divw: M(ax[rw,implicit], dx[rw,implicit], rm16) => 0x66 + 0xF7 /6 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
idivb_m
idivb: M(ax[rw,implicit], rm8) => 0xF6 /7 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
idivl_m
idivl: M(eax[rw,implicit], edx[rw,implicit], rm32) => 0xF7 /7 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
idivq_m
idivq: M(rax[rw,implicit], rdx[rw,implicit], rm64) => REX.W + 0xF7 /7 [_64b] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
idivw_m
idivw: M(ax[rw,implicit], dx[rw,implicit], rm16) => 0x66 + 0xF7 /7 [_64b | compat] has_trap // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulb_m
imulb: M(ax[rw,implicit], rm8) => 0xF6 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imull_m
imull: M(eax[rw,implicit], edx[w,implicit], rm32) => 0xF7 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imull_rm
imull: RM(r32[rw], rm32) => 0x0F + 0xAF [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imull_rmi
imull: RMI(r32[w], rm32, imm32) => 0x69 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imull_rmi_sxb
imull: RMI_SXB(r32[w], rm32, imm8[sxl]) => 0x6B ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulq_m
imulq: M(rax[rw,implicit], rdx[w,implicit], rm64) => REX.W + 0xF7 /5 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulq_rm
imulq: RM(r64[rw], rm64) => REX.W + 0x0F + 0xAF [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulq_rmi_sxb
imulq: RMI_SXB(r64[w], rm64, imm8[sxq]) => REX.W + 0x6B ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulq_rmi_sxl
imulq: RMI_SXL(r64[w], rm64, imm32[sxq]) => REX.W + 0x69 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulw_m
imulw: M(ax[rw,implicit], dx[w,implicit], rm16) => 0x66 + 0xF7 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulw_rm
imulw: RM(r16[rw], rm16) => 0x66 + 0x0F + 0xAF [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulw_rmi
imulw: RMI(r16[w], rm16, imm16) => 0x66 + 0x69 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
imulw_rmi_sxb
imulw: RMI_SXB(r16[w], rm16, imm8[sxw]) => 0x66 + 0x6B ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcb_mi
lock_adcb: MI(m8[rw], imm8) => 0xF0 + 0x80 /2 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcb_mr
lock_adcb: MR(m8[rw], r8) => 0xF0 + 0x10 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcl_mi
lock_adcl: MI(m32[rw], imm32) => 0xF0 + 0x81 /2 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcl_mi_sxb
lock_adcl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /2 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcl_mr
lock_adcl: MR(m32[rw], r32) => 0xF0 + 0x11 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcq_mi_sxb
lock_adcq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /2 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcq_mi_sxl
lock_adcq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /2 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcq_mr
lock_adcq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x11 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcw_mi
lock_adcw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /2 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_adcw_mr
lock_adcw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x11 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addb_mi
lock_addb: MI(m8[rw], imm8) => 0xF0 + 0x80 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addb_mr
lock_addb: MR(m8[rw], r8) => 0xF0 + 0x00 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addl_mi
lock_addl: MI(m32[rw], imm32) => 0xF0 + 0x81 /0 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addl_mi_sxb
lock_addl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addl_mr
lock_addl: MR(m32[rw], r32) => 0xF0 + 0x01 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addq_mi_sxb
lock_addq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /0 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addq_mi_sxl
lock_addq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /0 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addq_mr
lock_addq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x01 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addw_mi
lock_addw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /0 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_addw_mr
lock_addw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x01 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andb_mi
lock_andb: MI(m8[rw], imm8) => 0xF0 + 0x80 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andb_mr
lock_andb: MR(m8[rw], r8) => 0xF0 + 0x20 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andl_mi
lock_andl: MI(m32[rw], imm32) => 0xF0 + 0x81 /4 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andl_mi_sxb
lock_andl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andl_mr
lock_andl: MR(m32[rw], r32) => 0xF0 + 0x21 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andq_mi_sxb
lock_andq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /4 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andq_mi_sxl
lock_andq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /4 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andq_mr
lock_andq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x21 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andw_mi
lock_andw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /4 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_andw_mr
lock_andw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x21 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orb_mi
lock_orb: MI(m8[rw], imm8) => 0xF0 + 0x80 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orb_mr
lock_orb: MR(m8[rw], r8) => 0xF0 + 0x08 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orl_mi
lock_orl: MI(m32[rw], imm32) => 0xF0 + 0x81 /1 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orl_mi_sxb
lock_orl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orl_mr
lock_orl: MR(m32[rw], r32) => 0xF0 + 0x09 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orq_mi_sxb
lock_orq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /1 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orq_mi_sxl
lock_orq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /1 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orq_mr
lock_orq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x09 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orw_mi
lock_orw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /1 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_orw_mr
lock_orw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x09 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbb_mi
lock_sbbb: MI(m8[rw], imm8) => 0xF0 + 0x80 /3 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbb_mr
lock_sbbb: MR(m8[rw], r8) => 0xF0 + 0x18 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbl_mi
lock_sbbl: MI(m32[rw], imm32) => 0xF0 + 0x81 /3 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbl_mi_sxb
lock_sbbl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /3 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbl_mr
lock_sbbl: MR(m32[rw], r32) => 0xF0 + 0x19 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbq_mi_sxb
lock_sbbq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /3 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbq_mi_sxl
lock_sbbq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /3 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbq_mr
lock_sbbq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x19 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbw_mi
lock_sbbw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /3 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_sbbw_mr
lock_sbbw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x19 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subb_mi
lock_subb: MI(m8[rw], imm8) => 0xF0 + 0x80 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subb_mr
lock_subb: MR(m8[rw], r8) => 0xF0 + 0x28 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subl_mi
lock_subl: MI(m32[rw], imm32) => 0xF0 + 0x81 /5 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subl_mi_sxb
lock_subl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subl_mr
lock_subl: MR(m32[rw], r32) => 0xF0 + 0x29 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subq_mi_sxb
lock_subq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /5 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subq_mi_sxl
lock_subq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /5 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subq_mr
lock_subq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x29 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subw_mi
lock_subw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /5 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_subw_mr
lock_subw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x29 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorb_mi
lock_xorb: MI(m8[rw], imm8) => 0xF0 + 0x80 /6 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorb_mr
lock_xorb: MR(m8[rw], r8) => 0xF0 + 0x30 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorl_mi
lock_xorl: MI(m32[rw], imm32) => 0xF0 + 0x81 /6 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorl_mi_sxb
lock_xorl: MI_SXB(m32[rw], imm8[sxl]) => 0xF0 + 0x83 /6 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorl_mr
lock_xorl: MR(m32[rw], r32) => 0xF0 + 0x31 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorq_mi_sxb
lock_xorq: MI_SXB(m64[rw], imm8[sxq]) => 0xF0 + REX.W + 0x83 /6 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorq_mi_sxl
lock_xorq: MI_SXL(m64[rw], imm32[sxq]) => 0xF0 + REX.W + 0x81 /6 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorq_mr
lock_xorq: MR(m64[rw], r64) => 0xF0 + REX.W + 0x31 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorw_mi
lock_xorw: MI(m16[rw], imm16) => 0xF0 + 0x66 + 0x81 /6 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lock_xorw_mr
lock_xorw: MR(m16[rw], r16) => 0xF0 + 0x66 + 0x31 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lzcntl_rm
lzcntl: RM(r32[w], rm32) => 0xF3 + 0x0F + 0xBD /r [_64b | compat | lzcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lzcntq_rm
lzcntq: RM(r64[w], rm64) => 0xF3 + REX.W + 0x0F + 0xBD /r [_64b | lzcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
lzcntw_rm
lzcntw: RM(r16[w], rm16) => 0xF3 + 0x66 + 0x0F + 0xBD /r [_64b | compat | lzcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
maxpd_a
maxpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x5F /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
maxps_a
maxps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x5F /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
maxsd_a
maxsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x5F /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
maxss_a
maxss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x5F /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
minpd_a
minpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x5D /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
minps_a
minps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x5D /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
minsd_a
minsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x5D /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
minss_a
minss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x5D /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movapd_a
movapd: A(xmm1[w], xmm_m128[align]) => 0x66 + 0x0F + 0x28 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movapd_b
movapd: B(xmm_m128[w,align], xmm1) => 0x66 + 0x0F + 0x29 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movaps_a
movaps: A(xmm1[w], xmm_m128[align]) => 0x0F + 0x28 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movaps_b
movaps: B(xmm_m128[w,align], xmm1) => 0x0F + 0x29 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movd_a
movd: A(xmm1[w], rm32) => 0x66 + 0x0F + 0x6E /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movd_b
movd: B(rm32[w], xmm2) => 0x66 + 0x0F + 0x7E /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movdqa_a
movdqa: A(xmm1[w], xmm_m128[align]) => 0x66 + 0x0F + 0x6F /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movdqa_b
movdqa: B(xmm_m128[w,align], xmm1) => 0x66 + 0x0F + 0x7F /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movdqu_a
movdqu: A(xmm1[w], xmm_m128) => 0xF3 + 0x0F + 0x6F /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movdqu_b
movdqu: B(xmm_m128[w], xmm1) => 0xF3 + 0x0F + 0x7F /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movmskpd_rm
movmskpd: RM(r32[w], xmm2) => 0x66 + 0x0F + 0x50 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movmskps_rm
movmskps: RM(r32[w], xmm2) => 0x0F + 0x50 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movq_a
movq: A(xmm1[w], rm64) => 0x66 + REX.W + 0x0F + 0x6E /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movq_b
movq: B(rm64[w], xmm2) => 0x66 + REX.W + 0x0F + 0x7E /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movsd_a_m
movsd: A_M(xmm1[w], m32) => 0xF2 + 0x0F + 0x10 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movsd_a_r
movsd: A_R(xmm1[rw], xmm2) => 0xF2 + 0x0F + 0x10 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movsd_c_m
movsd: C_M(m64[w], xmm1) => 0xF2 + 0x0F + 0x11 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movss_a_m
movss: A_M(xmm1[w], m32) => 0xF3 + 0x0F + 0x10 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movss_a_r
movss: A_R(xmm1[rw], xmm2) => 0xF3 + 0x0F + 0x10 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movss_c_m
movss: C_M(m64[w], xmm1) => 0xF3 + 0x0F + 0x11 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movupd_a
movupd: A(xmm1[w], xmm_m128) => 0x66 + 0x0F + 0x10 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movupd_b
movupd: B(xmm_m128[w], xmm1) => 0x66 + 0x0F + 0x11 /r [_64b | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movups_a
movups: A(xmm1[w], xmm_m128) => 0x0F + 0x10 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
movups_b
movups: B(xmm_m128[w], xmm1) => 0x0F + 0x11 /r [_64b | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulb_m
mulb: M(ax[rw,implicit], rm8) => 0xF6 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mull_m
mull: M(eax[rw,implicit], edx[w,implicit], rm32) => 0xF7 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulpd_a
mulpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x59 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulps_a
mulps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x59 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulq_m
mulq: M(rax[rw,implicit], rdx[w,implicit], rm64) => REX.W + 0xF7 /4 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulsd_a
mulsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x59 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulss_a
mulss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x59 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
mulw_m
mulw: M(ax[rw,implicit], dx[w,implicit], rm16) => 0x66 + 0xF7 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
negb_m
negb: M(rm8[rw]) => 0xF6 /3 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
negl_m
negl: M(rm32[rw]) => 0xF7 /3 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
negq_m
negq: M(rm64[rw]) => REX.W + 0xF7 /3 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
negw_m
negw: M(rm16[rw]) => 0x66 + 0xF7 /3 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
notb_m
notb: M(rm8[rw]) => 0xF6 /2 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
notl_m
notl: M(rm32[rw]) => 0xF7 /2 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
notq_m
notq: M(rm64[rw]) => REX.W + 0xF7 /2 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
notw_m
notw: M(rm16[rw]) => 0x66 + 0xF7 /2 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orb_i
orb: I(al[rw], imm8) => 0x0C ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orb_mi
orb: MI(rm8[rw], imm8) => 0x80 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orb_mr
orb: MR(rm8[rw], r8) => 0x08 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orb_rm
orb: RM(r8[rw], rm8) => 0x0A /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orl_i
orl: I(eax[rw], imm32) => 0x0D id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orl_mi
orl: MI(rm32[rw], imm32) => 0x81 /1 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orl_mi_sxb
orl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orl_mr
orl: MR(rm32[rw], r32) => 0x09 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orl_rm
orl: RM(r32[rw], rm32) => 0x0B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orpd_a
orpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x56 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orps_a
orps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x56 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orq_i_sxl
orq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x0D id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orq_mi_sxb
orq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /1 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orq_mi_sxl
orq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /1 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orq_mr
orq: MR(rm64[rw], r64) => REX.W + 0x09 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orq_rm
orq: RM(r64[rw], rm64) => REX.W + 0x0B /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orw_i
orw: I(ax[rw], imm16) => 0x66 + 0x0D iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orw_mi
orw: MI(rm16[rw], imm16) => 0x66 + 0x81 /1 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orw_mr
orw: MR(rm16[rw], r16) => 0x66 + 0x09 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
orw_rm
orw: RM(r16[rw], rm16) => 0x66 + 0x0B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddb_a
paddb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xFC /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddd_a
paddd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xFE /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddq_a
paddq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD4 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddsb_a
paddsb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xEC /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddsw_a
paddsw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xED /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddusb_a
paddusb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDC /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddusw_a
paddusw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDD /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
paddw_a
paddw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xFD /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pand_a
pand: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDB /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pandn_a
pandn: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDF /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pextrb_a
pextrb: A(rm32[w], xmm2, imm8) => 0x66 + 0x0F + 0x3A 0x14 /r ib [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pextrd_a
pextrd: A(rm32[w], xmm2, imm8) => 0x66 + 0x0F + 0x3A 0x16 /r ib [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pextrq_a
pextrq: A(rm64[w], xmm2, imm8) => 0x66 + REX.W + 0x0F + 0x3A 0x16 /r ib [_64b | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pextrw_a
pextrw: A(r32[w], xmm2, imm8) => 0x66 + 0x0F + 0xC5 /r ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pextrw_b
pextrw: B(rm32[w], xmm2, imm8) => 0x66 + 0x0F + 0x3A 0x15 /r ib [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
phaddd_a
phaddd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x02 /r [_64b | compat | ssse3] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
phaddw_a
phaddw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x01 /r [_64b | compat | ssse3] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pinsrb_a
pinsrb: A(xmm1[rw], rm32, imm8) => 0x66 + 0x0F + 0x3A 0x20 /r ib [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pinsrd_a
pinsrd: A(xmm1[rw], rm32, imm8) => 0x66 + 0x0F + 0x3A 0x22 /r ib [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pinsrq_a
pinsrq: A(xmm1[rw], rm64, imm8) => 0x66 + REX.W + 0x0F + 0x3A 0x22 /r ib [_64b | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pinsrw_a
pinsrw: A(xmm1[rw], rm32, imm8) => 0x66 + 0x0F + 0xC4 /r ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxsb_a
pmaxsb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3C /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxsd_a
pmaxsd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3D /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxsw_a
pmaxsw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xEE /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxub_a
pmaxub: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDE /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxud_a
pmaxud: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3F /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmaxuw_a
pmaxuw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3E /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminsb_a
pminsb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x38 /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminsd_a
pminsd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x39 /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminsw_a
pminsw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xEA /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminub_a
pminub: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xDA /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminud_a
pminud: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3B /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pminuw_a
pminuw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x3A /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmovmskb_rm
pmovmskb: RM(r32[w], xmm2) => 0x66 + 0x0F + 0xD7 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmuldq_a
pmuldq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x28 /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmulhrsw_a
pmulhrsw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x0B /r [_64b | compat | ssse3] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmulhuw_a
pmulhuw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE4 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmulhw_a
pmulhw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE5 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmulld_a
pmulld: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x38 0x40 /r [_64b | compat | sse41] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmullw_a
pmullw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD5 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pmuludq_a
pmuludq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF4 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
popcntl_rm
popcntl: RM(r32[w], rm32) => 0xF3 + 0x0F + 0xB8 /r [_64b | compat | popcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
popcntq_rm
popcntq: RM(r64[w], rm64) => 0xF3 + REX.W + 0x0F + 0xB8 /r [_64b | popcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
popcntw_rm
popcntw: RM(r16[w], rm16) => 0xF3 + 0x66 + 0x0F + 0xB8 /r [_64b | compat | popcnt] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
por_a
por: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xEB /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pslld_a
pslld: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF2 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pslld_b
pslld: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x72 /6 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psllq_a
psllq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF3 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psllq_b
psllq: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x73 /6 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psllw_a
psllw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF1 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psllw_b
psllw: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x71 /6 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrad_a
psrad: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE2 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrad_b
psrad: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x72 /4 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psraw_a
psraw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE1 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psraw_b
psraw: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x71 /4 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrld_a
psrld: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD2 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrld_b
psrld: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x72 /2 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrlq_a
psrlq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD3 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrlq_b
psrlq: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x73 /2 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrlw_a
psrlw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD1 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psrlw_b
psrlw: B(xmm1[rw], imm8) => 0x66 + 0x0F + 0x71 /2 ib [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubb_a
psubb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF8 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubd_a
psubd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xFA /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubq_a
psubq: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xFB /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubsb_a
psubsb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE8 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubsw_a
psubsw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xE9 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubusb_a
psubusb: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD8 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubusw_a
psubusw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xD9 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
psubw_a
psubw: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xF9 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpckhbw_a
punpckhbw: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x68 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpckhdq_a
punpckhdq: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x6A /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpckhqdq_a
punpckhqdq: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x6D /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpckhwd_a
punpckhwd: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x69 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpcklbw_a
punpcklbw: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x60 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpckldq_a
punpckldq: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x62 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpcklqdq_a
punpcklqdq: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x6C /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
punpcklwd_a
punpcklwd: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x61 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
pxor_a
pxor: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0xEF /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolb_mc
rolb: MC(rm8[rw], cl) => 0xD2 /0 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolb_mi
rolb: MI(rm8[rw], imm8) => 0xC0 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
roll_mc
roll: MC(rm32[rw], cl) => 0xD3 /0 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
roll_mi
roll: MI(rm32[rw], imm8) => 0xC1 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolq_mc
rolq: MC(rm64[rw], cl) => REX.W + 0xD3 /0 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolq_mi
rolq: MI(rm64[rw], imm8) => REX.W + 0xC1 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolw_mc
rolw: MC(rm16[rw], cl) => 0x66 + 0xD3 /0 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rolw_mi
rolw: MI(rm16[rw], imm8) => 0x66 + 0xC1 /0 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorb_mc
rorb: MC(rm8[rw], cl) => 0xD2 /1 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorb_mi
rorb: MI(rm8[rw], imm8) => 0xC0 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorl_mc
rorl: MC(rm32[rw], cl) => 0xD3 /1 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorl_mi
rorl: MI(rm32[rw], imm8) => 0xC1 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorq_mc
rorq: MC(rm64[rw], cl) => REX.W + 0xD3 /1 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorq_mi
rorq: MI(rm64[rw], imm8) => REX.W + 0xC1 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorw_mc
rorw: MC(rm16[rw], cl) => 0x66 + 0xD3 /1 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
rorw_mi
rorw: MI(rm16[rw], imm8) => 0x66 + 0xC1 /1 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarb_mc
sarb: MC(rm8[rw], cl) => 0xD2 /7 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarb_mi
sarb: MI(rm8[rw], imm8) => 0xC0 /7 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarl_mc
sarl: MC(rm32[rw], cl) => 0xD3 /7 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarl_mi
sarl: MI(rm32[rw], imm8) => 0xC1 /7 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarq_mc
sarq: MC(rm64[rw], cl) => REX.W + 0xD3 /7 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarq_mi
sarq: MI(rm64[rw], imm8) => REX.W + 0xC1 /7 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarw_mc
sarw: MC(rm16[rw], cl) => 0x66 + 0xD3 /7 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sarw_mi
sarw: MI(rm16[rw], imm8) => 0x66 + 0xC1 /7 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbb_i
sbbb: I(al[rw], imm8) => 0x1C ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbb_mi
sbbb: MI(rm8[rw], imm8) => 0x80 /3 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbb_mr
sbbb: MR(rm8[rw], r8) => 0x18 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbb_rm
sbbb: RM(r8[rw], rm8) => 0x1A /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbl_i
sbbl: I(eax[rw], imm32) => 0x1D id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbl_mi
sbbl: MI(rm32[rw], imm32) => 0x81 /3 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbl_mi_sxb
sbbl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /3 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbl_mr
sbbl: MR(rm32[rw], r32) => 0x19 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbl_rm
sbbl: RM(r32[rw], rm32) => 0x1B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbq_i_sxl
sbbq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x1D id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbq_mi_sxb
sbbq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /3 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbq_mi_sxl
sbbq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /3 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbq_mr
sbbq: MR(rm64[rw], r64) => REX.W + 0x19 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbq_rm
sbbq: RM(r64[rw], rm64) => REX.W + 0x1B /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbw_i
sbbw: I(ax[rw], imm16) => 0x66 + 0x1D iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbw_mi
sbbw: MI(rm16[rw], imm16) => 0x66 + 0x81 /3 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbw_mr
sbbw: MR(rm16[rw], r16) => 0x66 + 0x19 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sbbw_rm
sbbw: RM(r16[rw], rm16) => 0x66 + 0x1B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlb_mc
shlb: MC(rm8[rw], cl) => 0xD2 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlb_mi
shlb: MI(rm8[rw], imm8) => 0xC0 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldl_mrc
shldl: MRC(rm32[rw], r32, cl) => 0x0F + 0xA5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldl_mri
shldl: MRI(rm32[rw], r32, imm8) => 0x0F + 0xA4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldq_mrc
shldq: MRC(rm64[rw], r64, cl) => REX.W + 0x0F + 0xA5 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldq_mri
shldq: MRI(rm64[rw], r64, imm8) => REX.W + 0x0F + 0xA4 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldw_mrc
shldw: MRC(rm16[rw], r16, cl) => 0x66 + 0x0F + 0xA5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shldw_mri
shldw: MRI(rm16[rw], r16, imm8) => 0x66 + 0x0F + 0xA4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shll_mc
shll: MC(rm32[rw], cl) => 0xD3 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shll_mi
shll: MI(rm32[rw], imm8) => 0xC1 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlq_mc
shlq: MC(rm64[rw], cl) => REX.W + 0xD3 /4 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlq_mi
shlq: MI(rm64[rw], imm8) => REX.W + 0xC1 /4 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlw_mc
shlw: MC(rm16[rw], cl) => 0x66 + 0xD3 /4 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shlw_mi
shlw: MI(rm16[rw], imm8) => 0x66 + 0xC1 /4 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrb_mc
shrb: MC(rm8[rw], cl) => 0xD2 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrb_mi
shrb: MI(rm8[rw], imm8) => 0xC0 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrl_mc
shrl: MC(rm32[rw], cl) => 0xD3 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrl_mi
shrl: MI(rm32[rw], imm8) => 0xC1 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrq_mc
shrq: MC(rm64[rw], cl) => REX.W + 0xD3 /5 [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrq_mi
shrq: MI(rm64[rw], imm8) => REX.W + 0xC1 /5 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrw_mc
shrw: MC(rm16[rw], cl) => 0x66 + 0xD3 /5 [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
shrw_mi
shrw: MI(rm16[rw], imm8) => 0x66 + 0xC1 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sqrtpd_a
sqrtpd: A(xmm1[w], xmm_m128[align]) => 0x66 + 0x0F + 0x51 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sqrtps_a
sqrtps: A(xmm1[w], xmm_m128[align]) => 0x0F + 0x51 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sqrtsd_a
sqrtsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x51 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
sqrtss_a
sqrtss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x51 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subb_i
subb: I(al[rw], imm8) => 0x2C ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subb_mi
subb: MI(rm8[rw], imm8) => 0x80 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subb_mr
subb: MR(rm8[rw], r8) => 0x28 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subb_rm
subb: RM(r8[rw], rm8) => 0x2A /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subl_i
subl: I(eax[rw], imm32) => 0x2D id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subl_mi
subl: MI(rm32[rw], imm32) => 0x81 /5 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subl_mi_sxb
subl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /5 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subl_mr
subl: MR(rm32[rw], r32) => 0x29 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subl_rm
subl: RM(r32[rw], rm32) => 0x2B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subpd_a
subpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x5C /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subps_a
subps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x5C /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subq_i_sxl
subq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x2D id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subq_mi_sxb
subq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /5 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subq_mi_sxl
subq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /5 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subq_mr
subq: MR(rm64[rw], r64) => REX.W + 0x29 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subq_rm
subq: RM(r64[rw], rm64) => REX.W + 0x2B /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subsd_a
subsd: A(xmm1[rw], xmm_m64) => 0xF2 + 0x0F + 0x5C /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subss_a
subss: A(xmm1[rw], xmm_m32) => 0xF3 + 0x0F + 0x5C /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subw_i
subw: I(ax[rw], imm16) => 0x66 + 0x2D iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subw_mi
subw: MI(rm16[rw], imm16) => 0x66 + 0x81 /5 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subw_mr
subw: MR(rm16[rw], r16) => 0x66 + 0x29 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
subw_rm
subw: RM(r16[rw], rm16) => 0x66 + 0x2B /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
tzcntl_a
tzcntl: A(r32[w], rm32) => 0xF3 + 0x0F + 0xBC /r [_64b | compat | bmi1] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
tzcntq_a
tzcntq: A(r64[w], rm64) => 0xF3 + REX.W + 0x0F + 0xBC /r [_64b | bmi1] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
tzcntw_a
tzcntw: A(r16[w], rm16) => 0xF3 + 0x66 + 0x0F + 0xBC /r [_64b | compat | bmi1] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
unpckhps_a
unpckhps: A(xmm1[rw], xmm_m128) => 0x0F + 0x15 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
unpcklpd_a
unpcklpd: A(xmm1[rw], xmm_m128) => 0x66 + 0x0F + 0x14 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
unpcklps_a
unpcklps: A(xmm1[rw], xmm_m128) => 0x0F + 0x14 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
vaddpd_b
vaddpd: B(xmm1[w], xmm2, xmm_m128) => VEX.128.66.0F.WIG 0x58 [_64b | compat | avx] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
vaddps_b
vaddps: B(xmm1[w], xmm2, xmm_m128) => VEX.128.0F.WIG 0x58 [_64b | compat | avx] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorb_i
xorb: I(al[rw], imm8) => 0x34 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorb_mi
xorb: MI(rm8[rw], imm8) => 0x80 /6 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorb_mr
xorb: MR(rm8[rw], r8) => 0x30 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorb_rm
xorb: RM(r8[rw], rm8) => 0x32 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorl_i
xorl: I(eax[rw], imm32) => 0x35 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorl_mi
xorl: MI(rm32[rw], imm32) => 0x81 /6 id [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorl_mi_sxb
xorl: MI_SXB(rm32[rw], imm8[sxl]) => 0x83 /6 ib [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorl_mr
xorl: MR(rm32[rw], r32) => 0x31 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorl_rm
xorl: RM(r32[rw], rm32) => 0x33 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorpd_a
xorpd: A(xmm1[rw], xmm_m128[align]) => 0x66 + 0x0F + 0x57 /r [_64b | compat | sse2] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorps_a
xorps: A(xmm1[rw], xmm_m128[align]) => 0x0F + 0x57 /r [_64b | compat | sse] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorq_i_sxl
xorq: I_SXL(rax[rw], imm32[sxq]) => REX.W + 0x35 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorq_mi_sxb
xorq: MI_SXB(rm64[rw], imm8[sxq]) => REX.W + 0x83 /6 ib [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorq_mi_sxl
xorq: MI_SXL(rm64[rw], imm32[sxq]) => REX.W + 0x81 /6 id [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorq_mr
xorq: MR(rm64[rw], r64) => REX.W + 0x31 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorq_rm
xorq: RM(r64[rw], rm64) => REX.W + 0x33 /r [_64b] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorw_i
xorw: I(ax[rw], imm16) => 0x66 + 0x35 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorw_mi
xorw: MI(rm16[rw], imm16) => 0x66 + 0x81 /6 iw [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorw_mr
xorw: MR(rm16[rw], r16) => 0x66 + 0x31 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14
xorw_rm
xorw: RM(r16[rw], rm16) => 0x66 + 0x33 /r [_64b | compat] // cranelift/assembler-x64/meta/src/generate/inst.rs:14