cranelift::prelude

Module types

Expand description

Common types for the Cranelift code generator.

Structs§

  • The type of an SSA value.

Constants§

  • A 16-bit floating point type represented in the IEEE 754-2008 binary16 interchange format. This corresponds to the :c:type:_Float16 type in most C implementations. WARNING: f16 support is a work-in-progress and is incomplete
  • A 32-bit floating point type represented in the IEEE 754-2008 binary32 interchange format. This corresponds to the :c:type:float type in most C implementations.
  • A 64-bit floating point type represented in the IEEE 754-2008 binary64 interchange format. This corresponds to the :c:type:double type in most C implementations.
  • A SIMD vector with 2 lanes containing a f16 each.
  • A SIMD vector with 4 lanes containing a f16 each.
  • A SIMD vector with 8 lanes containing a f16 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing f16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing f16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing f16 bits each.
  • A SIMD vector with 16 lanes containing a f16 each.
  • A SIMD vector with 32 lanes containing a f16 each.
  • A dynamically-scaled SIMD vector with a minimum of 16 lanes containing f16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 32 lanes containing f16 bits each.
  • A SIMD vector with 2 lanes containing a f32 each.
  • A SIMD vector with 4 lanes containing a f32 each.
  • A SIMD vector with 8 lanes containing a f32 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing f32 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing f32 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing f32 bits each.
  • A SIMD vector with 16 lanes containing a f32 each.
  • A dynamically-scaled SIMD vector with a minimum of 16 lanes containing f32 bits each.
  • A SIMD vector with 2 lanes containing a f64 each.
  • A SIMD vector with 4 lanes containing a f64 each.
  • A SIMD vector with 8 lanes containing a f64 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing f64 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing f64 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing f64 bits each.
  • A 128-bit floating point type represented in the IEEE 754-2008 binary128 interchange format. This corresponds to the :c:type:_Float128 type in most C implementations. WARNING: f128 support is a work-in-progress and is incomplete
  • A SIMD vector with 2 lanes containing a f128 each.
  • A SIMD vector with 4 lanes containing a f128 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing f128 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing f128 bits each.
  • An integer type with 8 bits. WARNING: arithmetic on 8bit integers is incomplete
  • A SIMD vector with 2 lanes containing a i8 each.
  • A SIMD vector with 4 lanes containing a i8 each.
  • A SIMD vector with 8 lanes containing a i8 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing i8 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing i8 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing i8 bits each.
  • A SIMD vector with 16 lanes containing a i8 each.
  • A SIMD vector with 32 lanes containing a i8 each.
  • A SIMD vector with 64 lanes containing a i8 each.
  • A dynamically-scaled SIMD vector with a minimum of 16 lanes containing i8 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 32 lanes containing i8 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 64 lanes containing i8 bits each.
  • An integer type with 16 bits. WARNING: arithmetic on 16bit integers is incomplete
  • An integer type with 32 bits.
  • An integer type with 64 bits.
  • A SIMD vector with 2 lanes containing a i16 each.
  • A SIMD vector with 4 lanes containing a i16 each.
  • A SIMD vector with 8 lanes containing a i16 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing i16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing i16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing i16 bits each.
  • A SIMD vector with 16 lanes containing a i16 each.
  • A SIMD vector with 32 lanes containing a i16 each.
  • A dynamically-scaled SIMD vector with a minimum of 16 lanes containing i16 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 32 lanes containing i16 bits each.
  • A SIMD vector with 2 lanes containing a i32 each.
  • A SIMD vector with 4 lanes containing a i32 each.
  • A SIMD vector with 8 lanes containing a i32 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing i32 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing i32 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing i32 bits each.
  • A SIMD vector with 16 lanes containing a i32 each.
  • A dynamically-scaled SIMD vector with a minimum of 16 lanes containing i32 bits each.
  • A SIMD vector with 2 lanes containing a i64 each.
  • A SIMD vector with 4 lanes containing a i64 each.
  • A SIMD vector with 8 lanes containing a i64 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing i64 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing i64 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 8 lanes containing i64 bits each.
  • An integer type with 128 bits.
  • A SIMD vector with 2 lanes containing a i128 each.
  • A SIMD vector with 4 lanes containing a i128 each.
  • A dynamically-scaled SIMD vector with a minimum of 2 lanes containing i128 bits each.
  • A dynamically-scaled SIMD vector with a minimum of 4 lanes containing i128 bits each.
  • Not a valid type. Can’t be loaded or stored. Can’t be part of a SIMD vector.