Module inst 

This module defines aarch64-specific machine instruction types.

Modules

args

AArch64 ISA definitions: instruction arguments.

emit

AArch64 ISA: binary code emission.

imms

AArch64 ISA definitions: immediate constants.

Structs

ASIMDFPModImm

Advanced SIMD modified immediate as used by the vector variant of FMOV.

ASIMDMovModImm

Advanced SIMD modified immediate as used by MOVI/MVNI.

FPULeftShiftImm

Floating-point unit immediate left shift.

FPURightShiftImm

Floating-point unit immediate right shift.

Imm12

A shifted immediate value in ‘imm12’ format: supports 12 bits, shifted left by 0 or 12 places.

ImmLogic

An immediate for logical instructions.

ImmShift

An immediate for shift instructions.

MoveWideConst

A 16-bit immediate for a MOVZ instruction, with a {0,16,32,48}-bit shift.

NZCV

An immediate that represents the NZCV flags.

ReturnCallInfo

Additional information for return_call[_ind] instructions, left out of line to lower the size of the Inst enum.

SImm9

a 9-bit signed offset.

SImm7Scaled

A signed, scaled 7-bit offset.

ShiftOpAndAmt

A shift operator with an amount, guaranteed to be within range.

ShiftOpShiftImm

A shift operator amount.

UImm5

An unsigned 5-bit immediate.

UImm12Scaled

An unsigned, scaled 12-bit offset.

Enums

ALUOp

Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 1209.

ALUOp3

Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 1247.

AMode

Internal type AMode: defined at src/isa/aarch64/inst.isle line 1393.

APIKey

Internal type APIKey: defined at src/isa/aarch64/inst.isle line 2046.

AtomicRMWLoopOp

Internal type AtomicRMWLoopOp: defined at src/isa/aarch64/inst.isle line 2030.

AtomicRMWOp

Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 2015.

BitOp

Internal type BitOp: defined at src/isa/aarch64/inst.isle line 1371.

BranchTarget

A branch target. Either unresolved (basic-block index) or resolved (offset from end of current instruction).

BranchTargetType

Internal type BranchTargetType: defined at src/isa/aarch64/inst.isle line 2059.

Cond

Condition for conditional branches.

CondBrKind

The kind of conditional branch: the common-case-optimized “reg-is-zero” / “reg-is-nonzero” variants, or the generic one that tests the machine condition codes.

ExtendOp

An extend operator for a register.

FPUOp1

Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 1673.

FPUOp2

Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 1683.

FPUOp3

Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 1694.

FPUOpRI

A floating-point unit (FPU) operation with two args, a register and an immediate.

FPUOpRIMod

A floating-point unit (FPU) operation with two args, a register and an immediate that modifies its dest (so takes that input value as a separate virtual register).

FpuRoundMode

Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1734.

FpuToIntOp

Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 1707.

Inst

Internal type MInst: defined at src/isa/aarch64/inst.isle line 9.

IntToFpuOp

Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1720.

LabelUse

Different forms of label references for different instruction formats.

MemLabel

A reference to some memory address.

MoveWideOp

Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 1259.

OperandSize

Type used to communicate the operand size of a machine instruction, as AArch64 has 32- and 64-bit variants of many instructions (and integer registers).

PairAMode

Internal type PairAMode: defined at src/isa/aarch64/inst.isle line 1507.

ScalarSize

Type used to communicate the size of a scalar SIMD & FP operand.

ShiftOp

A shift operator for a register or immediate.

TestBitAndBranchKind

Internal type TestBitAndBranchKind: defined at src/isa/aarch64/inst.isle line 1542.

VecALUModOp

Internal type VecALUModOp: defined at src/isa/aarch64/inst.isle line 1845.

VecALUOp

Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1756.

VecExtendOp

Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1747.

VecLanesOp

Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1988.

VecMisc2

Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1858.

VecPairOp

Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1969.

VecRRLongOp

Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1919.

VecRRNarrowOp

Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1934.

VecRRPairLongOp

Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1977.

VecRRRLongModOp

Internal type VecRRRLongModOp: defined at src/isa/aarch64/inst.isle line 1960.

VecRRRLongOp

Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1948.

VecShiftImmModOp

Internal type VecShiftImmModOp: defined at src/isa/aarch64/inst.isle line 2008.

VecShiftImmOp

Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1997.

VectorSize

Type used to communicate the size of a vector operand.

Constants

PINNED_REG

The pinned register on this architecture. It must be the same as Spidermonkey’s HeapReg, as found in this file. https://searchfox.org/mozilla-central/source/js/src/jit/arm64/Assembler-arm64.h#103

Functions

fp_reg

Get a reference to the frame pointer (x29).

link_reg

Get a reference to the link register (x30).

pinned_reg

Get a reference to the pinned register (x21).

pretty_print_ireg

pretty_print_reg

pretty_print_reg_sized

pretty_print_vreg_element

pretty_print_vreg_scalar

pretty_print_vreg_vector

show_ireg_sized

If ireg denotes an Int-classed reg, make a best-effort attempt to show its name at the 32-bit size.

show_vreg_element

Show an indexed vector element.

show_vreg_scalar

Show a vector register used in a scalar context.

show_vreg_vector

Show a vector register.

spilltmp_reg

Get a reference to the first temporary, sometimes “spill temporary”, register. This register is used to compute the address of a spill slot when a direct offset addressing mode from FP is not sufficient (+/- 2^11 words). We exclude this register from regalloc and reserve it for this purpose for simplicity; otherwise we need a multi-stage analysis where we first determine how many spill slots we have, then perhaps remove the reg from the pool and recompute regalloc.

stack_reg

Get a reference to the stack-pointer register.

tmp2_reg

Get a reference to the second temp register. We need this in some edge cases where we need both the spilltmp and another temporary.

vreg

Get a reference to a V-register (vector/FP register).

writable_fp_reg

Get a writable reference to the frame pointer.

writable_link_reg

Get a writable reference to the link register.

writable_spilltmp_reg

Get a writable reference to the spilltmp reg.

writable_stack_reg

Get a writable reference to the stack-pointer register.

writable_tmp2_reg

Get a writable reference to the tmp2 reg.

writable_vreg

Get a writable reference to a V-register.

writable_xreg

Get a writable reference to an X-register.

writable_zero_reg

Get a writable reference to the zero-register (this discards a result).

xreg

Get a reference to an X-register (integer register). Do not use this for xsp / xzr; we have two special registers for those.

zero_reg

Get a reference to the zero-register.